Error when using an alias to slice a signal

[maleiter]

If the discrete_range of a slice_name is an alias of a discrete_subtype_indication, NVC outputs "Error: invalid use of alias ...". If I add 'range to the alias, it works.

Here is a minimal example:

library ieee;
use ieee.std_logic_1164.all;

entity AliasRangeExample is
end entity AliasRangeExample;

architecture Bhv of AliasRangeExample is

    signal A: std_ulogic_vector(31 downto 0);
    signal B,C,D: std_ulogic_vector(7 downto 0);

    subtype aRange is natural range 7 downto 0;
    alias aRangeAlias is aRange;
begin
    B <= A(aRange); -- okay
    C <= A(aRangeAlias'range); -- okay
    D <= A(aRangeAlias); -- ** Error: invalid use of alias ARANGEALIAS
end architecture;

[nickg]

Should be fixed now, thanks.