External name in port map causes segmentation fault during elaboration

[yikkrubz]

Elaborating D causes a segmentation fault.

nvc --std=08 -a D.vhd nvc --std=08 -e D

Caught signal 11 (SIGSEGV) [address=0x0, ip=0x10573e751]

[0x1056735f4] signal_handler+0x3d4 [0x7ff81451137c] (/usr/lib/system/libsystem_platform.dylib) _sigtramp+0x1c [0x10573e752] lower_external_name+0x182 [0x1057213b6] lower_expr+0x906 [0x105746793] lower_build_wait_cb+0x43 [0x105752c1f] lower_instance+0x2ebf [0x1056f0445] elab_lower+0x55 [0x1056f6076] elab_architecture+0xcc6 [0x1056f082e] elab_stmts+0x27e [0x1056f6090] elab_architecture+0xce0 [0x1056eeea9] elab_top_level+0x599 [0x1056edfc6] elab+0x4a6 [0x105669181] process_command+0x1061 [0x105667b09] main+0x579

Please report this bug at https://github.com/nickg/nvc/issues

nvc 1.12-devel (1.11.0.r132.gf4380803) (Using LLVM 17.0.6)

Macos: 14.3.1 (intel)

D.vhd

library ieee; use ieee.std_logic_1164.all;

entity A is port ( clk : in std_logic; e : in std_logic; f : out std_logic ); end A;

architecture rtl of A is begin end architecture;

library ieee; use ieee.std_logic_1164.all;

entity B is port ( clk : in std_logic; f : in std_logic ); end B;

architecture rtl of B is begin end architecture;

library ieee; use ieee.std_logic_1164.all;

entity C is port ( clk : in std_logic; e : in std_logic ); end C;

architecture rtl of C is signal f : std_logic; begin A : entity work.A(rtl) port map ( clk => clk, e => e, f => f ); end architecture;

library ieee; use ieee.std_logic_1164.all;

entity D is end D;

architecture sim of D is signal clk : std_logic; signal e : std_logic; begin G : entity work.C(rtl) port map ( clk => clk, e => e );

H : entity work.B(rtl) port map ( clk => clk, f => << signal G.f : std_logic >> ); end architecture;