nickg / nvc

VHDL compiler and simulator
https://www.nickg.me.uk/nvc/
GNU General Public License v3.0
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Relax hidden declaration to warning #870

Closed Anselmo95 closed 3 months ago

Anselmo95 commented 3 months ago

Hello,

While analysing the code below NVC errors out because the generic is hidden by the variable inside the process. While I understand that this is not a good practice would it be possible to have an option, maybe --relaxed or another one, to reduce this error to just a warning ?

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity ent is
generic (
    SEED1 : natural
);
port (
    clk : in std_logic
);
end entity ent;

architecture arch of ent is
begin
    process(clk)
        variable seed1 : natural := SEED1;
    begin
    end process;
end architecture arch;
Anselmo95 commented 3 months ago

Thanks a lot for the change !

nickg commented 3 months ago

This error comes from the rules in LRM section 12.3 "Visibility": an object declaration hides all homographs from the start of its declaration but is not itself visible until the end of the declaration. So it's illegal to reference an object with a given name inside a declaration with the same name.

Anyway I can skip this check with --relaxed, which actually just restores the behaviour before #733.