Add error message when attempting to use external signals in procedure prior to elaboration

[a-panella]

Scenario: attempting to access external signals within a procedure declared in declarative region causes NVC to crash with a SIGMAPERR

As far as I understand, attempting to do this (access external signals within a procedure) is not valid VHDL anyway - it would be helpful to have a check for this and display an error message that clarifies this

MRE:

-- entity declaration above
architecture rtl of some_entity is 

  procedure do_something(constant a : in integer range 0 to 3) is 
    -- `some_ext_signal` is out of scope as we have not elaborated yet, NVC should report this instead of crashing
    alias some_ext_signal is <<signal .top.some_instance.some_signal : std_logic>>;
  begin
     --drive the signal, whatever
     ...
  end procedure;
begin
...
end rtl;

[nickg]

It now reports this:

** Error: cannot create driver for external name as subprogram PROC [] is not contained 
          within a process statement
   > ../test/sem/issue884.vhd:7
   |
 7 |         << signal .issue884.uut.x : integer >> <= 42;  -- Error
   |         ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^