nickg / nvc

VHDL compiler and simulator
https://www.nickg.me.uk/nvc/
GNU General Public License v3.0
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Segfault with cyclic signal assignments #885

Closed leksiso closed 1 month ago

leksiso commented 1 month ago

Hello again,

I ran into a segfault when I accidentally created a zero-time loop. The iteration limit check doesn't fire here for some reason.

Here's the reduced code demonstrating the problem:

library ieee;
use ieee.std_logic_1164.all;

entity first is
    port (
        a : in std_logic_vector(1 downto 0);
        b : out std_logic_vector(1 downto 0)
    );
end entity;

architecture rtl of first is
    signal c : std_logic;

begin
    b <= a;
    c <= a(0);

end architecture;
library ieee;
use ieee.std_logic_1164.all;

entity second is
    port (
        a : in std_logic_vector(1 downto 0);
        b : out std_logic_vector(1 downto 0) := "00"
    );
end entity;

architecture rtl of second is
begin
    b <= a;
end architecture;
library ieee;
use ieee.std_logic_1164.all;

entity test is
end entity test;

architecture arch of test is
    signal b : std_logic_vector(1 downto 0);
    signal a : std_logic_vector(1 downto 0);

begin
    first : entity work.first(rtl)
        port map(
            b => b,
            a => a
        );

    second : entity work.second(rtl)
        port map(
            a => b,
            b => a
        );

end architecture;
nickg commented 1 month ago

The crash actually happens when it's trying to print the iteration limit message. Now it reports:

** Fatal: 0ms+10000: limit of 10000 delta cycles reached
    > /home/nick/nvc/test/regress/issue885.vhd:46
    |
 12 |     signal c : std_logic;
    |            ^ driver for signal C is active
 ...
 28 |         b : out std_logic_vector(1 downto 0) := "00"
    |         ^ driver for port B is active
 ...
 46 |     signal b : std_logic_vector(1 downto 0);
    |            ^ driver for signal B is active
    |
    = Note: you can increase this limit with --stop-delta