External name in call to falling_edge is not considered as a name denoting a signal

[yikkrubz]

Nvc does not accept an external name in a wait until falling_edge statement. The code is accepted by ghdl and Questa.

nvc 1.13-devel (1.12.0.r119.g4978acf1) (Using LLVM 18.1.3)

macos 14.5 (intel)

nvc -a C.vhd ** Error: actual for formal S with class SIGNAL must be a name denoting a signal

C.vhd:63	63	wait until falling_edge(<< signal B_INST.i : std_logic >>); -- not accepted by nvc	^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ actual designator is not a name

= Help: IEEE Std 1076-2008 section 4.2.2.3 "Signal parameters"

C.vhd

library ieee; use ieee.std_logic_1164.all;

entity A is port ( clk : in std_logic; d : in std_logic; e : out std_logic := '1' ); end A;

architecture rtl of A is begin end architecture;

library ieee; use ieee.std_logic_1164.all;

entity B is port ( f : in std_logic; g : in std_logic ); end B;

architecture rtl of B is

signal clk : std_logic; signal h : std_logic; signal i : std_logic; begin

A_INST : entity work.A(rtl) port map ( clk => clk, d => h, e => i );

end architecture;

library ieee; use ieee.std_logic_1164.all; use std.env.finish;

entity C is end C;

architecture sim of C is signal clk : std_logic := '1'; begin

clk <= not clk after 10 ns;

B_INST : entity work.B(rtl) port map ( f => clk, g => '0' );

process begin wait until falling_edge(<< signal B_INST.i : std_logic >>); -- not accepted by nvc -- wait until << signal B_INST.i : std_logic >> = '0'; -- accepted by nvc

wait for 10 ns;

finish;

end process; end architecture;