Closed wolftrax84 closed 13 years ago
Ran correctly at 50 MHz in Post-Route and Testing Simulation. Used 219 clock cycles between start and done signals.
Behavioral Timing Samples: START: 2540 ns DONE: 6900 ns TOTAL: 218 Clock cycles
START: 981,940 ns DONE: 986,300 ns TOTAL: 218 Clock Cycles
bits.c