Lag Window

[thrawn117]

Test Lag Window. Test this one 2nd.

[jpj79]

 Time resolution is 1 ps
 # onerror resume
 # wave add /
 # run 1000 ns
 Simulator is doing circuit initialization process.
 ERROR: Too many words specified in datafile 1lag_window_in.out
 ERROR: Too many words specified in datafile 1lag_window_out.out
 Block Memory Generator CORE Generator module lag_window_test_v.lag Mem.Scratch_mem.inst.blk_mem_gen_v4_3_inst is using a behavioral model for simulation which will not precisely model memory collision behavior.
 Finished circuit initialization process.

[jpj79]

Post-Route Error: ERROR:HDLCompiler:559 - "C:/ECE4532/Lag_Window/../Project_Testing/Top Level Scratch Memory/Scratch_Memory_Controller.v" Line 30: Could not find module/primitive .Turning on mult-threading, number of parallel sub-compilation jobs: 4 ERROR:Simulator:778 - Static elaboration of top level Verilog design unit(s) in library work failed

[thrawn117]

The "too many words" error is no concern really. It just means that the reg array we're reading the files into isn't big enough. Which is fine, because it's big enough to read in more than enough values for our tests. Hopefully Dr. Morris can clear up the Post-Route Error.

[jpj79]

After working extra time with Dr. Morris, Zach, and Cooper we have our first module completing the Post-Route Simulation. The output was with the corrected values but memory collisions are still apparent. Understanding the memory collisions is one thing I am working towards.

Memory Collision Error on X_ARAMB36_INTERNAL : lag_window_test_v.uut.\pipey.lagMem.Az_scratch_mem.BU2.U0.blk_mem_generator.valid.cstr.ramloop[1].ram.r.v5_noinit.ram.SDP.SINGLE_PRIM36.TDP .INT_RAMB.chk_for_col_msg at simulation time 2033.867 ns.
A read was performed on address 919x (hex) of port B while a write was requested to the same address on port A. The write will be successful however the read value on port B is unknown until the next CLKB cycle.
Memory Collision Error on X_ARAMB36_INTERNAL : lag_window_test_v.uut.\pipey.lagMem.Az_scratch_mem.BU2.U0.blk_mem_generator.valid.cstr.ramloop[0].ram.r.v5_noinit.ram.SDP.SINGLE_PRIM36.TDP .INT_RAMB.chk_for_col_msg at simulation time 2133.857 ns.
A read was performed on address 91ax (hex) of port B while a write was requested to the same address on port A. The write will be successful however the read value on port B is unknown until the next CLKB cycle.
Memory Collision Error on X_ARAMB36_INTERNAL : lag_window_test_v.uut.\pipey.lagMem.Az_scratch_mem.BU2.U0.blk_mem_generator.valid.cstr.ramloop[1].ram.r.v5_noinit.ram.SDP.SINGLE_PRIM36.TDP .INT_RAMB.chk_for_col_msg at simulation time 2133.867 ns.
A read was performed on address 91ax (hex) of port B while a write was requested to the same address on port A. The write will be successful however the read value on port B is unknown until the next CLKB cycle.
            2175 CORRECT:  r'[          0] = 55400000
            2210 CORRECT:  r'[          1] = 087d2f16
            2245 CORRECT:  r'[          2] = 00000000
            2280 CORRECT:  r'[          3] = 0fd66f00
            2315 CORRECT:  r'[          4] = e47e75e8
            2350 CORRECT:  r'[          5] = f2623baa
            2385 CORRECT:  r'[          6] = f85038ec
            2420 CORRECT:  r'[          7] = f86c520c
            2455 CORRECT:  r'[          8] = 00000000
            2490 CORRECT:  r'[          9] = 00000000
            2525 CORRECT:  r'[         10] = 00000000
Memory Collision Error on X_ARAMB36_INTERNAL : lag_window_test_v.uut.\pipey.lagMem.Az_scratch_mem.BU2.U0.blk_mem_generator.valid.cstr.ramloop[0].ram.r.v5_noinit.ram.SDP.SINGLE_PRIM36.TDP .INT_RAMB.chk_for_col_msg at simulation time 3553.857 ns.
A read was performed on address 910x (hex) of port B while a write was requested to the same address on port A. The write will be successful however the read value on port B is unknown until the next CLKB cycle.
Memory Collision Error on X_ARAMB36_INTERNAL : lag_window_test_v.uut.\pipey.lagMem.Az_scratch_mem.BU2.U0.blk_mem_generator.valid.cstr.ramloop[1].ram.r.v5_noinit.ram.SDP.SINGLE_PRIM36.TDP .INT_RAMB.chk_for_col_msg at simulation time 3553.867 ns.
A read was performed on address 910x (hex) of port B while a write was requested to the same address on port A. The write will be successful however the read value on port B is unknown until the next CLKB cycle.

[thrawn117]

Closing this one since you finished testing.

[jpj79]

There is a few size mismatches that need to be fixed. I have them recorded and they will be a quick fix.

[jpj79]

Post-Route has generated a clean output at 50 MHz. I am closing this and will do further testing on it for data at different clock frequencies.

[jpj79]

Behavioral Timing Samples: START: 990 ns DONE: 2,630 ns TOTAL: 82 Clock cycles

START: 316,550 ns DONE: 318,190 ns TOTAL: 100 Clock Cycles

[anumariam]

How to solve the Block memory collision issue?I ran the same design in Xilinx ISE 12.4