nicyyyy / FPGA-CLAHE

Constrast limited adaptive histogram equlization based on Verilog
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[Synth 8-3380] loop condition does not converge after 2000 iterations #4

Open Enternal-w opened 2 months ago

Enternal-w commented 2 months ago

作者你好,在编译综合中我遇到一些问题不知道如何解决,在tb-clahe-top.v程序中的第97行, while(pixel_cnt < 32'd921600) begin start_num = {$random}%721 + 2; pause_num = {$random}%11 + 2; while(start_num > 1) begin start_num = start_num - 1;

(period);

     end
     while(pause_num > 1)
     begin
     pause_num = pause_num - 1;
     TVALID_in = 0;
     #(period);
     end
     TVALID_in = 1;
     end

出现了这样的错误,[Synth 8-3380] loop condition does not converge after 2000 iterations 不知道该如何解决 与此同时还有[Synth 8-6156] failed synthesizing module 'tb_CLAHE_top' [Common 17-69] Command failed: Vivado Synthesis failed 是操作有误还是程序需要修改呢,期待您的回复

nicyyyy commented 2 months ago

tb文件里是测试激励,是不可综合的喔。更换顶层文件试试

Enternal-w commented 2 months ago

感谢您的回复,早上这个问题解决了,还有个问题想问您的是,是不是再加一个IP核ram的就可以成功综合了,(目前已经成功综合),作为新手还有一些不太懂,tb里面读取的.bin文件是图像转化而来的吗,可以直接读取png或者bmp吗

---Original--- From: "Tsingyow @.> Date: Tue, Aug 13, 2024 13:40 PM To: @.>; Cc: @.**@.>; Subject: Re: [nicyyyy/FPGA-CLAHE] [Synth 8-3380] loop condition does notconverge after 2000 iterations (Issue #4)

tb文件里是测试激励,是不可综合的喔。更换顶层文件试试

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