Milestones for Midterm

[dralabeing]

Project extended to 14 week. New deadline for midterm completion and evaluation- Aug 3. Complete RTL-GDSII section "Running the Automatic RTL-GDSII flow" using design with key Flow stages using mem_1r1w.v. Sections Capture Quick Start Flow in the RTL-GDSII section. These must be done based on Guidelines for writing and Layout. Please have the Grammar and writing style independently reviewed. Mentors cannot spend additional time reviewing this for each piece of work. Refer here for details: https://github.com/armleo/OpenLane/issues/3

Introduction - Describe scope and a brief introduction. Also what users will learn from this Tutorial Scope Assumptions

Setting up the Environment

Platform Design Configuration Design Source Files RTL, Libraries Running The Automatic RTL-to-GDS Flow Design Goals - Complete the design flow from RTL-GDSII to meet timing and ensure that it is DRC, LVS clean Viewing Results (include for each stage) Flow stages (follow the layout in the QuickStart) Synthesis Design Exploration Floorplanning Power Planning and Analysis Placement CTS Global Routing .... Use openroad gui separately to show results for each stage in detail until we get a working GUI in OpenLane. Refer to the ORFS flow tutorial for GUI details. https://openroad.readthedocs.io/en/latest/tutorials/FlowTutorial.html# [View Result of the flow](https://nimradoc-openlane.readthedocs.io/en/latest/docs/source/flow_tutorial.html#view-result-of-the-flow) [Area](https://nimradoc-openlane.readthedocs.io/en/latest/docs/source/flow_tutorial.html#area) [Power](https://nimradoc-openlane.readthedocs.io/en/latest/docs/source/flow_tutorial.html#power) [Timing](https://nimradoc-openlane.readthedocs.io/en/latest/docs/source/flow_tutorial.html#timing) [Viewing Layout Result](https://nimradoc-openlane.readthedocs.io/en/latest/docs/source/flow_tutorial.html#viewing-layout-result)

[kareefardi]

Some feedback:

• Why are file extensions referred to as .def/ with a trailing slash ?
• Introduction and overview should be merged.
• Setting up the environment should point to installation guide
• I thought we agreed not to have area as a design goal?
• Timing is met after routing. Refer to the reports after routing not before that to show that timing is met
• Inconsistent usage of bullet lists
• Final gds directory not mentioned
• The area reported after synthesis is the total area of the gates used in the design. The floorplan isn't ready at this point. The design area mentioned as the goal should be captured in the floorplan reports or later stages
• There should be consistency in usage of openlane variables in code blocks (e.g. platform configuration code block doesn't have any syntax, timing goal block isn't proper tcl, etc.)
• I believe it is best to actually put the configuration of the design itself in the design configuration section
• In future iterations, I think there should be more samples of logs and reports. Sections of the logs themselves and the naming and ordering of the logs should be in the tutorial

[dralabeing]

Meeting review and other details to address for midterm: Follow layout discussed (missing synthesis exploration) Guidelines, English, writing style, spelling- please refer to guidelines again. Do not copy text from OpenROAD. This is a tutorial for OpenLane and must reflect that. Introduction- only one common one for all OL docs. - Get it from the OpenLane team @kareefardi for the sake of consistency and accuracy. Mention scope.:"You will learn how to set up and run the OpenLane flow from RTL to GDSII and generate a DRC, LVS clean layout. Update flow stages -Each box description should be brief and accurate. Results log picture should be a tree with important results files shown in relevant directories Add timing analysis post placement optimization (brief result showing timing path in GUI and report results)- A detailed analysis section (TBD later) will contain timing, congestion/heat map analysis Add placeholder, refer to flow.tcl command line arguments (in user guide) Add placeholder, refer to platform and design configuration variables (in user guide)

[dralabeing]

Getting Started This section assumes a clean and validated installation to execute RTL to GDSII flow of the design. This section describes the environment setup to run a design in both automatic and interactive mode.

mem_1r1w is a memory design used to run the flow in the tutorial.

"can be found" in text-> Find and replace with active voice e.g Refer to The libraries cell information can found here.-> Refer to the library information here:

RTL-GDSII - Not RTL to GDSII (Guidelines.....) In this section you will learn how to run the complete design flow from RTL-GDSII both in the interactive and automatic flow. <Does this design create compiled memories? If so, please include how this is generated in OL using DFFRAM or OpenRAM etc.

Remove Area goal Refer to .sdc constraints in the .sdc file with description of each constraint in there (clock period, setup, hold, false paths etc)

Running the automatic flow inside the docker (remove with): -> Make sure user is in the correct user directory, cd ..

Floorplanning not Floor Planning . Check the writing style and English across the document including Interactive mode: OpenLane run in a interactive mode by using -interactive where every steps of a design run by the user.->You can run OpenLane in an interactive mode for greater control for each step of the design flow as follows:

./flow.tcl -interactive A tcl shell will be opened where the OpenLane package is automatically sourced:-> use active voice... This opens an interactive TCl interpreter window.

% package required openlane Then, able to run the following main commands:-> Fix english

[vijayank88]

@nimra471 Please update your fork to latest commits from master and apply changes accordingly into flow turotrial

[kareefardi]

• STD_CELL_LIBRARY is not a path. It is simply the name.
• inline comments in tcl:
  • Do:

    set x "20" ;# this is a comment

  • Avoid:

    set x "20" # this is a comment

• explain the timing constraints in the sdc file
• missing link to "OpenLane Installation"
• avoid "the" OpenLane. It just OpenLane.
• Run Directory Structure: by a diagram for logs only.
  • the diagram has a lot of unnecessary white-space.
  • perhaps instead of a diagram, you might want to consider the output of tree command
  • In this section, you need to capture:
  • what to expect: for example, there are "X" folders (results, routing, etc..). and then each folder contains folders for each main stage of the flow and then what is the contents of these folders? what do these folders resemble ?
  • what do numbers prefix indicate? are they fixed?
  • where are the final views?
  • currently this captures some, but not all, of the above
• for synthesis exploration use -synth_explore

[dralabeing]

final gds name should match the design block name. klayout mem_1r1r.gds-> change this to mem_1r1w.gds

[nimra471]

@vijayank88 Done update the latest commit to the fork

[nimra471]

Project extended to 14 week. New deadline for midterm completion and evaluation- Aug 3. Complete RTL-GDSII section "Running the Automatic RTL-GDSII flow" using design with key Flow stages using mem_1r1w.v. Sections Capture Quick Start Flow in the RTL-GDSII section. These must be done based on Guidelines for writing and Layout. Please have the Grammar and writing style independently reviewed. Mentors cannot spend additional time reviewing this for each piece of work. Refer here for details: armleo#3

Introduction - Describe scope and a brief introduction. Also what users will learn from this Tutorial Scope Assumptions

Setting up the Environment Platform Design Configuration Design Source Files RTL, Libraries Running The Automatic RTL-to-GDS Flow Design Goals - Complete the design flow from RTL-GDSII to meet timing and ensure that it is DRC, LVS clean Viewing Results (include for each stage) Flow stages (follow the layout in the QuickStart) Synthesis Design Exploration Floorplanning Power Planning and Analysis Placement CTS Global Routing ....

Use openroad gui separately to show results for each stage in detail until we get a working GUI in OpenLane. Refer to the ORFS flow tutorial for GUI details. https://openroad.readthedocs.io/en/latest/tutorials/FlowTutorial.html#

View Result of the flow Area Power Timing Viewing Layout Result

Done

[nimra471]

Meeting review and other details to address for midterm: Follow layout discussed (missing synthesis exploration) Guidelines, English, writing style, spelling- please refer to guidelines again. Do not copy text from OpenROAD. This is a tutorial for OpenLane and must reflect that. Introduction- only one common one for all OL docs. - Get it from the OpenLane team @kareefardi for the sake of consistency and accuracy. Mention scope.:"You will learn how to set up and run the OpenLane flow from RTL to GDSII and generate a DRC, LVS clean layout. Update flow stages -Each box description should be brief and accurate. Results log picture should be a tree with important results files shown in relevant directories Add timing analysis post placement optimization (brief result showing timing path in GUI and report results)- A detailed analysis section (TBD later) will contain timing, congestion/heat map analysis Add placeholder, refer to flow.tcl command line arguments (in user guide) Add placeholder, refer to platform and design configuration variables (in user guide)

added synthesis exploration and updated according to the feedback.

[nimra471]

final gds name should match the design block name. klayout mem_1r1r.gds-> change this to mem_1r1w.gds

update the change

[nimra471]

• STD_CELL_LIBRARY is not a path. It is simply the name.

• inline comments in tcl:

  • Do:

  set x "20" ;# this is a comment

  • Avoid:

  set x "20" # this is a comment

• explain the timing constraints in the sdc file
• missing link to "OpenLane Installation"
• avoid "the" OpenLane. It just OpenLane.

• Run Directory Structure: by a diagram for logs only.

  • the diagram has a lot of unnecessary white-space.

  • perhaps instead of a diagram, you might want to consider the output of tree command

  • In this section, you need to capture:

  • what to expect: for example, there are "X" folders (results, routing, etc..). and then each folder contains folders for each main stage of the flow and then what is the contents of these folders? what do these folders resemble ?

  • what do numbers prefix indicate? are they fixed?

  • where are the final views?

  • currently this captures some, but not all, of the above

• for synthesis exploration use -synth_explore

updated the flow.tutorial with the given feedback

[nimra471]

Getting Started This section assumes a clean and validated installation to execute RTL to GDSII flow of the design. This section describes the environment setup to run a design in both automatic and interactive mode.

mem_1r1w is a memory design used to run the flow in the tutorial.

"can be found" in text-> Find and replace with active voice e.g Refer to The libraries cell information can found here.-> Refer to the library information here:

RTL-GDSII - Not RTL to GDSII (Guidelines.....) In this section you will learn how to run the complete design flow from RTL-GDSII both in the interactive and automatic flow. <Does this design create compiled memories? If so, please include how this is generated in OL using DFFRAM or OpenRAM etc.

Remove Area goal Refer to .sdc constraints in the .sdc file with description of each constraint in there (clock period, setup, hold, false paths etc)

Running the automatic flow inside the docker (remove with): -> Make sure user is in the correct user directory, cd ..

Floorplanning not Floor Planning . Check the writing style and English across the document including Interactive mode: OpenLane run in a interactive mode by using -interactive where every steps of a design run by the user.->You can run OpenLane in an interactive mode for greater control for each step of the design flow as follows:

./flow.tcl -interactive A tcl shell will be opened where the OpenLane package is automatically sourced:-> use active voice... This opens an interactive TCl interpreter window.

% package required openlane Then, able to run the following main commands:-> Fix english

Done with the given changes