Do you have a bit-flipping Verilog？

[zengqh12138]

Do you have a bit-flipping Verilog？Thanks

[nirajnsharma]

It is in BSV, from which you can generate Verilog RTL. The compiler is available in open-source at:

https://github.com/B-Lang-org/bsc

Regards, Niraj

On Mon, 1 Jun 2020 at 08:07, zengqh12138 notifications@github.com wrote:

Do you have a bit-flipping Verilog？Thanks

— You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub https://github.com/nirajnsharma/ee705-ldpc/issues/1, or unsubscribe https://github.com/notifications/unsubscribe-auth/ABT4TY2B4UYG5WWZNT643O3RUMH5FANCNFSM4NPOGEPQ .

[zengqh12138]

Thank you very much indeed. Have you used this compiler?  I don't understand.I am in a hurry, could you help me to generate it?  I used to use MATLAB simulation before, and I want to generate the bit rollover algorithm.Looking forward to your reply.  Thank you

------------------ Original ------------------ From:  "Niraj Sharma";<notifications@github.com>; Send time: Monday, Jun 1, 2020 1:07 PM To: "nirajnsharma/ee705-ldpc"<ee705-ldpc@noreply.github.com>; Cc: "zengqh"<942092189@qq.com>; "Author"<author@noreply.github.com>; Subject:  Re: [nirajnsharma/ee705-ldpc] Do you have a bit-flipping Verilog？ (#1)

It is in BSV, from which you can generate Verilog RTL. The compiler is available in open-source at:

https://github.com/B-Lang-org/bsc

Regards, Niraj

On Mon, 1 Jun 2020 at 08:07, zengqh12138 <notifications@github.com> wrote:

> Do you have a bit-flipping Verilog？Thanks > > — > You are receiving this because you are subscribed to this thread. > Reply to this email directly, view it on GitHub > <https://github.com/nirajnsharma/ee705-ldpc/issues/1&gt;, or unsubscribe > <https://github.com/notifications/unsubscribe-auth/ABT4TY2B4UYG5WWZNT643O3RUMH5FANCNFSM4NPOGEPQ&gt; > . >

— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub, or unsubscribe.