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nmi-leipzig / sim-x-pll

Verilog based simulation modell for 7 Series PLL
ISC License
11 stars 2 forks source link

Verilator support? #11

Closed xobs closed 4 years ago

xobs commented 4 years ago

Verilator is a very fast-but-messy simulator that can be used to simulate entire CPUs at a rate such that they can be used interactively. To the best of my knowledge, it currently has no good solution to multiple clock domains. Additionally, it is not easy to simulate Xilinx designs in Verilator.

How can we add Verilator support to this project, in order to support simulating more complex designs?

tmahlburg commented 4 years ago

From what I can see, Verilator needs synthesizable Verilog as an input. This project is by design not synthesizable, since it is only meant for simulation. There are a lot of delay-statements in there, for example. Is this conception of mine correct?

xobs commented 4 years ago

That does seem to be the case. Thanks for looking at it.