WIP: Clocked EXG

[larsbrinkhoff]

This is a work in progress. I'm submitting a pull request to get some comments. I haven't tested the EXG instruction yet!

This is approximately how I see most clocked instructions being implemented: they can do something every other clock cycle, and if so do ADD_CYCLE(2). Intermediate stages don't need different labels in instr_state. Correct prefetch handling is done by doing it at the correct cycle inside the instruction.

[stefanberndtsson]

Yes, I've started looking at MOVE now, and I thought of the same thing really. In the case of EXG, labels don't make much sense, since there are no multiple paths. With MOVE it depends quite a bit on EA, so it's not a straight path for the entire instruction.

MOVE can't do "on cycle 4 read word, on cycle 8 write word", except in the simple case of MOVE (A0),(A1) of course. The labels make sense with MOVE.

MOVE.W D0,D1 : INITIAL -> FINISHED MOVE.W D0,(A0) : INITIAL -> WrWORD -> FINISHED MOVE.L D0,4(A0) : INITIAL -> EA_FETCH -> WrHiWORD -> WrLoWORD -> FINISHED

...and so on.

[larsbrinkhoff]

Ok, that makes sense.

Did you do something to start a bus cycle and wait for its completion?

[stefanberndtsson]

No, I use (or abuse ?) the cpu->icycle, which is set via ADD_CYCLE() to essentially delay the next entry into the instruction by that many cycles.

So each cpu_step_cycle() loop will either decrement icycle (if it was > 0) or if it was 0, enter the instruction again for the next section.

Take a write to PSG for example. The instruction will add 4 cycles for the write, then psg_write_byte() will also do ADD_CYCLE(2), which for that case makes icycle 6, delaying the next state execution slightly longer than the normal 4 cycles. This simulates the waitstates from slower I/O without breaking the old cpu.

This also makes the old instructions (that set the full icycle in its only pass) work as if it was a state-machine with only a single state.

[larsbrinkhoff]

It seems to work now.

[larsbrinkhoff]

Thinking a bit more about what you wrote above, it's actually somewhat brittle to make the state machine rely on cycles since instruction start. If a memory access adds move cycles, the cycle numbers will be off, and intermediate states may be missed.

So I'll fix EXG to not use cycle numbers.

[larsbrinkhoff]

By the way, is this normal when using -K?

DEBUG: Triggering BUS ERROR

[stefanberndtsson]

Yes, another bit of debug I forgot to remove. Clocked has its own exception calls, and that BUS ERROR is the one triggered when TOS is checking for a Blitter during boot.