Medres broken since 23e23 (clocked only)

[stefanberndtsson]

Something in https://github.com/nocrew/ostis/commit/23e239461dfc26c35e89a74a389b5816385c0ec1 broke medres. It's not reading data properly since then.

https://github.com/nocrew/ostis/commit/5aa12aa4190f0fd60e0760d6d044d48bce057157 works fine.

This is only an issue with -K

[larsbrinkhoff]

That's strange. These vertical patterns typically happens when some timing is off in the shifter logic to copy data from IR to RR, or from upper RRs to lower.

This shifter is quite finicky with regards to timing; there are a few small windows where copying needs to happen. But obviously the 23e2394 change doesn't touch the shifter. There may be a more fundamental problem in the clocked CPU, which is bad.

The good news is that there is no problem in my current shifter branch, which should be due for merging soon.

[larsbrinkhoff]

It works for me with the latest master, d29ef59.

[stefanberndtsson]

Yes, this seems ok now.

[stefanberndtsson]

Ok, reopening this for a place to gather issues regarding shifter.

BIG_DEMO.MSA Loadscreen shows, main demoscreen flickers once, then disappears. Border colours remain. Both with and without -K

PHALANX.MSA Menu works with border F1 works with border F3 complete flickering (both -K and not) F6 disappears with -K, flickering border without

XXX_INT.MSA Big bendy, no border Scrolly, no border without -K, disappears fairly quickly (but not immediately) with -K Personal msg, no border without -K, disappears with -K

SWEDISH1.MSA Everything same both with and without -K Menu, no border F2, fullscreen not working, screen disappears after that (press space for second screen) F3, screen disappears

[stefanberndtsson]

Desktop

Ok, here is part of a log-dump of a desktop case (i.e. working). This loads data into IR and then RR properly.

Vsync

CLOCK [0050561968]: SHFT: DE = 0

First DE=1

CLOCK [0050594792]: MMU0: DE
CLOCK [0050594792]: SHFT: DE = 1

DE=0 => DE=1 : 32824 clocks

First DE to first RR

CLOCK [0050594792]: MMU0: DE
CLOCK [0050594792]: SHFT: DE = 1
CLOCK [0050594793]: MMU0: DE
CLOCK [0050594793]: SHFT: DE = 1
CLOCK [0050594794]: MMU0: DE
CLOCK [0050594794]: SHFT: DE = 1
CLOCK [0050594795]: MMU0: DE
CLOCK [0050594795]: SHFT: DE = 1
CLOCK [0050594796]: MMU0: DE
CLOCK [0050594796]: SHFT: DE = 1
CLOCK [0050594797]: MMU0: DE
CLOCK [0050594797]: SHFT: DE = 1
CLOCK [0050594798]: MMU0: DE
CLOCK [0050594798]: SHFT: DE = 1
CLOCK [0050594798]: MMU0: LOAD
CLOCK [0050594798]: SHFT: LOAD IR0: 0000
CLOCK [0050594799]: MMU0: DE
CLOCK [0050594799]: SHFT: DE = 1
CLOCK [0050594800]: MMU0: DE
CLOCK [0050594800]: SHFT: DE = 1
CLOCK [0050594801]: MMU0: DE
CLOCK [0050594801]: SHFT: DE = 1
CLOCK [0050594802]: MMU0: DE
CLOCK [0050594802]: SHFT: DE = 1
CLOCK [0050594802]: MMU0: LOAD
CLOCK [0050594802]: SHFT: LOAD IR1: 0000
CLOCK [0050594803]: MMU0: DE
CLOCK [0050594803]: SHFT: DE = 1
CLOCK [0050594804]: MMU0: DE
CLOCK [0050594804]: SHFT: DE = 1
CLOCK [0050594805]: MMU0: DE
CLOCK [0050594805]: SHFT: DE = 1
CLOCK [0050594806]: MMU0: DE
CLOCK [0050594806]: SHFT: DE = 1
CLOCK [0050594806]: MMU0: LOAD
CLOCK [0050594806]: SHFT: LOAD IR2: 0000
CLOCK [0050594807]: MMU0: DE
CLOCK [0050594807]: SHFT: DE = 1
CLOCK [0050594808]: MMU0: DE
CLOCK [0050594808]: SHFT: DE = 1
CLOCK [0050594809]: MMU0: DE
CLOCK [0050594809]: SHFT: DE = 1
CLOCK [0050594810]: MMU0: DE
CLOCK [0050594810]: SHFT: DE = 1
CLOCK [0050594810]: MMU0: LOAD
CLOCK [0050594810]: SHFT: LOAD IR3: 0000
CLOCK [0050594811]: MMU0: DE
CLOCK [0050594811]: SHFT: DE = 1
CLOCK [0050594811]: SHFT: Load RR: 0000 0000 0000 0000

[stefanberndtsson]

Big Demo

And here is the same part for Big Demo, where LOAD is missed all the time for some reason.

Vsync

CLOCK [0054087600]: SHFT: DE = 0

First DE=1

CLOCK [0054120424]: MMU0: DE
CLOCK [0054120424]: SHFT: DE = 1

DE=0 => DE=1 : 32824 clocks

First DE to first RR (not happening):

CLOCK [0054120424]: MMU0: DE
CLOCK [0054120424]: SHFT: DE = 1
CLOCK [0054120425]: MMU0: DE
CLOCK [0054120425]: SHFT: DE = 1
CLOCK [0054120426]: MMU0: DE
CLOCK [0054120426]: SHFT: DE = 1
CLOCK [0054120427]: MMU0: DE
CLOCK [0054120427]: SHFT: DE = 1
CLOCK [0054120428]: MMU0: DE
CLOCK [0054120428]: SHFT: DE = 1
CLOCK [0054120429]: MMU0: DE
CLOCK [0054120429]: SHFT: DE = 1
CLOCK [0054120430]: MMU0: DE
CLOCK [0054120430]: SHFT: DE = 1
CLOCK [0054120430]: MMU0: LOAD
CLOCK [0054120430]: SHFT: LOAD missed: 8000
CLOCK [0054120431]: MMU0: DE
CLOCK [0054120431]: SHFT: DE = 1
CLOCK [0054120432]: MMU0: DE
CLOCK [0054120432]: SHFT: DE = 1
CLOCK [0054120433]: MMU0: DE
CLOCK [0054120433]: SHFT: DE = 1
CLOCK [0054120434]: MMU0: DE
CLOCK [0054120434]: SHFT: DE = 1
CLOCK [0054120434]: MMU0: LOAD
CLOCK [0054120434]: SHFT: LOAD missed: 7fff
CLOCK [0054120435]: MMU0: DE
CLOCK [0054120435]: SHFT: DE = 1
CLOCK [0054120436]: MMU0: DE
CLOCK [0054120436]: SHFT: DE = 1
CLOCK [0054120437]: MMU0: DE
CLOCK [0054120437]: SHFT: DE = 1
CLOCK [0054120438]: MMU0: DE
CLOCK [0054120438]: SHFT: DE = 1
CLOCK [0054120438]: MMU0: LOAD
CLOCK [0054120438]: SHFT: LOAD missed: 0000
CLOCK [0054120439]: MMU0: DE
CLOCK [0054120439]: SHFT: DE = 1
CLOCK [0054120440]: MMU0: DE
CLOCK [0054120440]: SHFT: DE = 1
CLOCK [0054120441]: MMU0: DE
CLOCK [0054120441]: SHFT: DE = 1
CLOCK [0054120442]: MMU0: DE
CLOCK [0054120442]: SHFT: DE = 1
CLOCK [0054120442]: MMU0: LOAD
CLOCK [0054120442]: SHFT: LOAD missed: 0000
CLOCK [0054120443]: MMU0: DE
CLOCK [0054120443]: SHFT: DE = 1
CLOCK [0054120444]: MMU0: DE
CLOCK [0054120444]: SHFT: DE = 1
CLOCK [0054120445]: MMU0: DE
CLOCK [0054120445]: SHFT: DE = 1
CLOCK [0054120446]: MMU0: DE
CLOCK [0054120446]: SHFT: DE = 1
CLOCK [0054120446]: MMU0: LOAD
CLOCK [0054120446]: SHFT: LOAD missed: 0000
CLOCK [0054120447]: MMU0: DE
CLOCK [0054120447]: SHFT: DE = 1
CLOCK [0054120448]: MMU0: DE
CLOCK [0054120448]: SHFT: DE = 1
CLOCK [0054120449]: MMU0: DE
CLOCK [0054120449]: SHFT: DE = 1
CLOCK [0054120450]: MMU0: DE
CLOCK [0054120450]: SHFT: DE = 1
CLOCK [0054120450]: MMU0: LOAD
CLOCK [0054120450]: SHFT: LOAD missed: ffff
CLOCK [0054120451]: MMU0: DE
CLOCK [0054120451]: SHFT: DE = 1
CLOCK [0054120452]: MMU0: DE
CLOCK [0054120452]: SHFT: DE = 1
CLOCK [0054120453]: MMU0: DE
CLOCK [0054120453]: SHFT: DE = 1
CLOCK [0054120454]: MMU0: DE
CLOCK [0054120454]: SHFT: DE = 1
CLOCK [0054120454]: MMU0: LOAD
CLOCK [0054120454]: SHFT: LOAD missed: 0000
CLOCK [0054120455]: MMU0: DE
CLOCK [0054120455]: SHFT: DE = 1
CLOCK [0054120456]: MMU0: DE
CLOCK [0054120456]: SHFT: DE = 1
CLOCK [0054120457]: MMU0: DE
CLOCK [0054120457]: SHFT: DE = 1
CLOCK [0054120458]: MMU0: DE
CLOCK [0054120458]: SHFT: DE = 1
CLOCK [0054120458]: MMU0: LOAD
CLOCK [0054120458]: SHFT: LOAD missed: 0000

[stefanberndtsson]

loads in shifter.c is obviously being incremented far beyond 4. Just for the heck of it, I applied this patch:

diff --git a/shifter.c b/shifter.c
index aa65c66..b02916f 100644
--- a/shifter.c
+++ b/shifter.c
@@ -358,8 +358,10 @@ void shifter_load(WORD data)
   if(loads < 4) {
     CLOCK("LOAD IR%d: %04x", loads, data);
     IR[loads] = data;
-  } else
+  } else {
+    loads -= 1;
     CLOCK("LOAD missed: %04x", data);
+  }

   // "Loads" is incremented one cycle after LOAD, and the pixel
   // counter starts two more cycles after that.

This made Big Demo almost correct on the main screen (one 16pxl segment is black before the border).

It doesn't solve any of the others, but it does make them not disappear.

[larsbrinkhoff]

Thank you! This should speed up debugging. Some quick notes:

• loads should never go beyond 4, since it corresponds to a 4-bit shift register.
• But then, raising LOAD when loads already is 4 should never happen!
• I think there may be a problem in the previous scanline, so that loads is never reset to 0.
• I don't know why your patch works!

[larsbrinkhoff]

Duh, your patch works, because the code is looking for loads == 4!

The problem is that the previous scanline ends by loading IR0-2. I'm not sure if this is correct behavour for BIG Demo, but it certainly could happen.