Microcoded EA calculation

[larsbrinkhoff]

This is a state machine for EA calculation. It's inspired by microcode. There is an upc which is a microcode PC, and ucycles specifies the length of the microprogram.

The microengine operates on two primary "registers". ea_address is the accumulator for the effective address being calculated. ea_data is the final operand, and also holds intermediate values read from memory.

A little work is done up-front when the state machine is initialised. After that, the addressing modes are implemented using six microinstructions which all takes one microcycle (two CPU cycles):

• n does nothing,
• r reads one word (or byte) from memory,
• p fetches one word from the program (this should integrate with the prefetch registers),
• a transfers ea_data to ea_address,
• sa like a with sign-extension, and
• idx calculates the "indirect with index" addressing mode.

Byte and long operands are supported by masking the final result, or running the program two more microcyles, respectively.

[stefanberndtsson]

Should read low word and read high word be different microcodes (and the same for write)? Maybe that's just unnecessary.

[larsbrinkhoff]

Should read low word and read high word be different microcodes

Don't know! They might, or they might not. If you read the current version carefully, you can see that the r microop works for both reading a byte, a word, or a long, depending on context.

I don't know why I did that. But it's not written in stone.

[larsbrinkhoff]

Added support for writing back the result in a typical read-modify-write instruction. This works by using ea_address from the reading phase.

[larsbrinkhoff]

Maybe some microcode explanation is in order.

static uop_t index_uops[] = { n, p, idx, r, n, r, n };

This is the microprogram for the indexed addressing mode. Before the microcode ea_address is initialised to the value of the base address register. The Yacht table specifies "n np nr" for this mode, so the microprogram begins with an n. The order inside the bus cycles are reversed from the Yacht notation, so the next step is a p fetch. This reads the extension word and stores it in ea_data. Then comes idx, which uses the extension word to add an offset and an index register to ea_address. Finally, there are one or two bus cycles to read from ea_address to ea_data.

[larsbrinkhoff]

This is verified by modifying CLR to use the new EA calculation and booting to the Desktop. This may not use all addressing modes, however, so there may well be bugs lurking.

Breaking news! Phalanx Demo F5 crashes with a bus error. BIG Demo no longer works.

Ok, I should debug this.

[larsbrinkhoff]

This implements most of #122.

[larsbrinkhoff]

Fixed BIG Demo. There was a bug in the absolute short addressing mode.

Phalanx F5 crashes in master too, so it's not a blocker for this PR.