Careful review of log files indicates that wait states appears where expected. I didn't change wait states between instructions when not running from RAM. I guess that can be done when prefetch has been improved.
Also verified with BIG Demo and Level 16 Full Screen Demo, without any regressions on clocked or old CPU mode.
Minor tweaks to how wait states are inserted.
Careful review of log files indicates that wait states appears where expected. I didn't change wait states between instructions when not running from RAM. I guess that can be done when prefetch has been improved.
Also verified with BIG Demo and Level 16 Full Screen Demo, without any regressions on clocked or old CPU mode.