This PR adds a new target amd-aiet-direct, directly references AIEVec passes (for eventual lowering of core code to chess LLVM IR) and also (simultaneously) vendors XCLBinGen.cpp from mlir-aie (second part used to be broken out in https://github.com/nod-ai/iree-amd-aie/pull/422 but on @newling's suggestion I squashed). Note, XCLBinGen and AIETargetDirect are basically carbon copies of what currently exists except AIETargetDirect doesn't shell out and calls aie2xclbin directly. Note also that XCLBinGen will undergo further revision up to for the chess backend (but that'll have to wait until I get home).
To test, I added some lines to print_ir_aie2xclbin.sh. I'm happy to bike shed this but probably not too hard.
This PR is part of a stack of PRs that refactor the dependency on MLIR-AIE. See https://github.com/nod-ai/iree-amd-aie/issues/430 for more information.
This PR adds a new target
amd-aiet-direct
, directly references AIEVec passes (for eventual lowering of core code to chess LLVM IR) and also (simultaneously) vendorsXCLBinGen.cpp
frommlir-aie
(second part used to be broken out in https://github.com/nod-ai/iree-amd-aie/pull/422 but on @newling's suggestion I squashed). Note,XCLBinGen
andAIETargetDirect
are basically carbon copies of what currently exists exceptAIETargetDirect
doesn't shell out and callsaie2xclbin
directly. Note also thatXCLBinGen
will undergo further revision up to for the chess backend (but that'll have to wait until I get home).To test, I added some lines to
print_ir_aie2xclbin.sh
. I'm happy to bike shed this but probably not too hard.