Recommendations on moving this forward

[milesfrain]

Hello, I'd like to help out with getting the VDS1022 supported in sigrok. Do you have any recommended next steps? I have your changes building and running, but I'm just getting flat line readings when attached to the 1khz test output. I'm wondering if the device channels are configured in GND coupling mode versus AC or DC, or maybe the channels are misconfigured in another way (voltage levels, triggering). One way I'm thinking to fix this is to setup wireshark monitoring of the Windows VM when toggling these channel settings, and double-checking that these commands are sent by sigrok.

I also skipped the firmware upload step after this command fails https://github.com/noopwafel/libsigrok/blob/master/src/hardware/owon-vds-tiny/protocol.c#L275:

vds_packed_cmd_response(sdi, 0x223, buffer, 1, 'E', &response);

I'm not sure where 0x233 originates. I couldn't find this anywhere in the decompiled source. Also, the device is working in the Windows VM, so I didn't want to risk messing-up the existing firmware.

The debug log seems to show working communication:

...
sr: [00:04.847196] session: bus: Received SR_DF_FRAME_BEGIN packet.
sr: [00:04.862227] owon-vds-tiny: receive_transfer(): status LIBUSB_SUCCESS / LIBUSB_TRANSFER_COMPLETED received 5211 bytes.
sr: [00:04.862304] owon-vds-tiny: got incoming packet
sr: [00:04.862392] session: bus: Received SR_DF_ANALOG packet (5098 samples).
"Querying config key samplerate is not allowed"
sr: [00:04.869545] owon-vds-tiny: receive_transfer(): status LIBUSB_SUCCESS / LIBUSB_TRANSFER_COMPLETED received 5211 bytes.
sr: [00:04.869601] owon-vds-tiny: got incoming packet
sr: [00:04.869684] session: bus: Received SR_DF_ANALOG packet (5098 samples).
"Querying config key samplerate is not allowed"
sr: [00:04.869958] session: bus: Received SR_DF_FRAME_END packet.
...

I've also been trying to get the vendor's java version working on Linux in https://github.com/tinwhisker/Owon-VDS1022/issues/6, but have been encountering some roadblocks. If we can get it to work from java source on linux, it should hopefully be straightforward to then achieve full sigrok support.

[noopwafel]

sorry for not keeping up communication about this :( I'm about to head to 35C3 unfortunately so I don't have much time right now, but we moved to a Python codebase for building an open source version because sigrok doesn't seem to be ideal for use as a "live" scope frontend (e.g. you can't change parameters on the fly and you can't easily add unsupported options). the firmware upload step is for the FPGA firmware, which you have to upload every time, not the MCU firmware - so it's expected that you won't get any data. would be great to see a wireshark capture, the FPGA firmware is pretty huge! do you actually have the FPGA firmware somewhere that sigrok can read it? I forget if I documented this. :/

[milesfrain]

Good note about the FPGA firmware. I originally thought a copy of this was saved on the MCU, rather than needing to be re-uploaded every time. I have the V3.7 firmware extracted from the .exe. Looks like your sigrok patch is expecting V3.5. I'm hoping either version is interchangeable. I don't have the hardware with me now to experiment with, but will report back if I'm still unable to log any data. Note for others, VDS1022_FPGA_V3.7.bin can be extracted from the .exe with 7-zip on linux.

7z e OWON_VDS_C2_1.0.30_Setup.exe

Let us know when the python codebase is ready for public eyes.

[noopwafel]

We're not going to have time to make this beautiful any time soon, so I pushed enough to make edge triggering work and our early Python work is now public at https://github.com/albert-spruyt/pyVds1022 - feel free to open issues and/or ask questions and/or hack on things, if it's useful to you. I do plan to do some work on it during the next week (e.g. right now the units are clearly bad, and I want to actually check everything against a signal generator), we'll see how that goes.