Closed StefanBruens closed 3 years ago
The work around for that is to pass regnr and value separately:
/* Set Display Clock Divide Ratio/ Oscillator Frequency */
write_reg(par, 0xD5);
write_reg(par, 0x80);
fbtft_device:
modprobe fbtft_device ... init=-1,0xd5,-1,0x80,...
Unfortunately the multiple write_reg fails in combination with 9 bit emulation. Each write_reg results in an independent 5 byte transfer (should be 9, but you corrected that in tinydrm), and the padding is interpreted as value.
The init sequence might actually work, will evaluate this.
Would you accept a patch to tinydrm with an additional "quirk" transfer mode, e.g mipi_dbi_typec1_command_no_dc ?
Would you accept a patch to tinydrm with an additional "quirk" transfer mode, e.g mipi_dbi_typec1_command_no_dc ?
No, because then it's not MIPI DBI anymore. Better add a new driver for the controller in question with the necessary protocol functions.
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Unfortunately SSD devices use two different concepts for register params:
e.g SSD1351:
e.g. SSD1306, SSD1225:
Currently fbtft_write_reg8_bus9 and fbtft_write_reg8_bus8 assume register params use DC=1.