MLIR flow

[gabrielrodcanal]

Hi, I intend to use this design to load AIE kernels generated in MLIR. As a first step, I was trying to generate the simple kernel you provide in https://github.com/nqdtan/vck5000_vivado_ulp/blob/2022.2/host_sw_with_aie/aie_core_elf/core.cc#L24

To my understanding, the MLIR code should look something like this:

module {
    %tile18_1 = AIE.tile(18, 1) 

    %buf = AIE.buffer(%tile18_1) { sym_name = "a18_1" } : memref<16xi32>

    %lock18_1_1 = AIE.lock(%tile18_1, 1) { sym_name = "lock_a18_1_1" }
    %core18_1 = AIE.core(%tile18_1) {
        // Locks init value is Release 0, so this will always succeed first
        AIE.useLock(%lock18_1_1, "Acquire", 0)

        %val = arith.constant 14 : i32 
               scf.for %idx = %min_idx to %max_idx step %step {
                    memref.store %val, %buf[idx] : memref<16xi32>
                }

        AIE.useLock(%lock18_1_1, "Release", 1)
        AIE.end
    } 
}

That code doesn't do exactly the same, but it's useful to ask the following questions:

1. How do I set up the same locks present in your code in MLIR?
2. You are fixing the buffer symbol in your C code to a memory position with https://github.com/nqdtan/vck5000_vivado_ulp/blob/d78ccee4d0e1ca3556e4b96fe12df145dde5ca1e/host_sw_with_aie/aie_core_elf/core.bcf#L5 How can I do the same?
3. The C code seems to be position independent in the AIE, as you fixed this in the host code to tile 18, 1. Is there a way to do the same in MLIR or is this a limitation of the AIE dialect?

[nqdtan]

For (1) and (2), you can run mlir-aie to generate a core program plus some header files contain some configuration data for the test you want to execute, and then you can integrate them here. Some information regarding specific locks and the buffer offsets could be found in mlir-aie source code. I would also try looking at a few test files and official AIE documents as well..

Regarding (3), there are tests that demonstrate how to link anAIE.core with an external core file, for example: tests/unit_tests/13_julia_fp/aie.mlir . I think there is also some MLIR op that let you define location agnostic core, but not sure about its current status now. Maybe try checking with mlir-aie repo?

[gabrielrodcanal]

Hi, So it seems the address of the buffer can be specified as an attribute in the aie.buffer operation. I'm not sure if the address is 0x38000? Could you point out to a reference on what the fields in the .bcf file mean? I couldn't find it. Also, could you please explain why this address in particular?

Thank you.