Cycle count decoders

[jotego]

I see many references to the cycle count state in the code. In C code it makes sense to carry the cycle count around as a decimal number. I wonder if it was done like that in the chip. Was there some sort of hot-one encoding used? Was the cycle count encoded in a 5-bit number or were decoded signals sent to relevant blocks?

For instance, in the LFO, it looks like it is only important to know if you are below 9, at zero or at the last one. It would be enough to get 3 signals from a central cycle counter instead of the 5-bit number and then decode it. Do you remember what the original approach was?

https://github.com/nukeykt/Nuked-OPLL/blob/3f25893fc0634f58e138967b403443e3c36a6658/opll.c#L1037

[nukeykt]

Internally YM2413 has cycle counter, which composed of two counters (first counts 0-5 and second 0-2 when first overflows). Output of these counters then are sent to the decoder matrix. Here's location of counters and matrix on VRC7 die http://www.siliconpr0n.com/map/konami/vrc_vii_053982/mz_mit20x/#x=3311&y=1592&z=5

[jotego]

Thank you. I had actually chosen the same two-approach counter as a result of analyzing the register numbering sequence. It is what makes sense. I'll keep that and I'll make the decoder with a hot-one barrel shift register as that is more economical in an FPGA than a logic decoder.