nvdla / hw

RTL, Cmodel, and testbench for NVDLA
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Problem RAM generation for synthesis #123

Closed Y159753 closed 6 years ago

Y159753 commented 6 years ago

To generate RAMs for the nvdla_small I face a little problem to set the option, in the integration doc it is written that : All functionality for a RAM can be inferred from the RAM name: RAM Arch_Depth X Width [_Options] Mux-Option Rev Mux-Option Required, fixed width field describing column mux options