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nvdla / hw

RTL, Cmodel, and testbench for NVDLA
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ram in /model and /synth ?? #125

Closed Y159753 closed 6 years ago

Y159753 commented 6 years ago

I am following the integration guide, but I face a problem concerning the replacement of the RAM by my local library wrappers.

I am not sure to understand what are the ram presented here : https://github.com/nvdla/hw/tree/nvdlav1/vmod/rams/model They are not instantiated in the verilog, but their functionalities are discussed in the documentation, with the list of their port, timing diagram etc.

On the contrary those ones : https://github.com/nvdla/hw/tree/nvdlav1/vmod/rams/synth Are instantiated all over the design, they are different to the ones in /model, and even have different ports, but there is no evocation of them in the doc ... what did I missed ?

Y159753 commented 6 years ago

well ok I found out, the verilogs in /synth are wrappers for the models of RAM in /synth. Each module in /synth is instantiating several Rams from /model.