csb_master: add missing 'valid' in core_resp_pvld

nvdla / hw

RTL, Cmodel, and testbench for NVDLA

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csb_master: add missing 'valid' in core_resp_pvld #129

Closed ghost closed 6 years ago

ghost commented 6 years ago

I am testing accessing CSB registers on Zynq UltraScale+ platform through AXI4 to APB bus bridge. I found that accessing CFGROM ends up with lockup state. If APB IP core is not configured to handle timeout, the entire system locks up, including JTAG and system reset / power cycle is required.

This modification should fix the problem.

jwise commented 6 years ago

Thanks! Good catch. Let me see if we have this fix internally already; if we do, I'll push that out, otherwise, I'll try to figure out how to integrate this direction...

jwise commented 6 years ago

I think we have an analogous fix from the internal repo that we've pushed out; a fix should be in the master branch now. Thanks again for the find!