The following table provides estimates for NVDLA configurations optimized
for the popular ResNet-50 neural network. The area figures given are
estimated synthesis area, and include all memories required; real area
results will vary based on foundry and libraries. In this example, no
on-chip SRAM is used. On-chip SRAM would be beneficial if available SDRAM
bandwidth is low. The open-source release of NVDLA has an performance
estimator tool available to explore the space of NVDLA designs, and
the impact on performance.
Power and performance in the following table are shown for a 1GHz frequency.
Power and performance for a given configuration can be varied though
adjustment of voltage and frquency.
Question about Silicon Cell Area (mm^2, 28nm) in synthesis, does the area include the rams in this path: hw/vmod/rams ?
below are contents from website: http://nvdla.org/primer.html
Example Area and Performance with NVDLA¶
The following table provides estimates for NVDLA configurations optimized for the popular ResNet-50 neural network. The area figures given are estimated synthesis area, and include all memories required; real area results will vary based on foundry and libraries. In this example, no on-chip SRAM is used. On-chip SRAM would be beneficial if available SDRAM bandwidth is low. The open-source release of NVDLA has an performance estimator tool available to explore the space of NVDLA designs, and the impact on performance.
Power and performance in the following table are shown for a 1GHz frequency. Power and performance for a given configuration can be varied though adjustment of voltage and frquency.