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RTL, Cmodel, and testbench for NVDLA
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How to Include DesignWare IPs In Synthesis #135

Closed silvaurus closed 6 years ago

silvaurus commented 6 years ago

Hi! I'm wondering how to include DesignWare IPs in Synthesis. Currently I got an error like this: Warning: Cannot find the design 'DW_lsd' in the library 'WORK'. (LBR-1) I have DesignWare installed under Design Compiler, but I'm not sure if there are any global variables I should set up, or if I should include DW's source code folder in EXTRA_RTL.

Thank you so much!

nodushiv commented 6 years ago

I assume that you aren't changing the `DESIGNWARE_NOEXIST RTL macro between build and synthesis.

What have you set as LINK_LIB in the configuration file?

If you have a standard DC install, you should see these libraries: ${DC_PATH}/../libraries/syn/dw_foundation.sldb ${DC_PATH}/../libraries/syn/gtech.db ${DC_PATH}/../libraries/syn/standard.sldb

You should add them to LINK_LIB if you dont already.

If that doesnt work - Can you post your DC log?

Thanks!

silvaurus commented 6 years ago

Thank you so much! It works now!

nodushiv commented 6 years ago

Thanks. Closing.