concurrent assignment to non-net signal in NV_NVDLA_CDMA_dc module

[JunningWu]

L1616, NV_NVDLA_CDMA_dc.v

dma_rsp_data_p0} = dma_rd_rsp_data;

dma_rsp_data_p0 is a reg type signal.

https://stackoverflow.com/questions/1809749/how-to-assign-a-value-to-an-output-reg-in-verilog/11234968#11234968

[JunningWu]

please close this issue. Thanks for mmaciag's commit.