nvdla / hw

RTL, Cmodel, and testbench for NVDLA
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Why memory.v is used ? #173

Open gowthar opened 6 years ago

gowthar commented 6 years ago

Hi, I am beginner to this project, and I have a basic question I noticed that there is a hw/verif/synth_tb/memory.v file available for nv_full version of nvdla. Is it like a memory module you guys attaching to the SRAM and DRAM interface of NVDLA in the top level ?. And I also noticed that nv_small doesn't have this file.?

nvhook commented 6 years ago

The module in memory.v is a functional model for simulating implementations using the external memory interfaces (DBBIF and SRAMIF).