RTL simulation and FPGA implement do not work, could anyone help me ?

[xivisi]

In rtl similation: 1, config A, git version: Latest commit 7cf6ad5 nv_small B, selfdefined testbench a), xilinx block ram relpace nv_rams nv_ram_rws no input output register; nv_ram_rwsp have input output register; nv_ram_rwst only input register; nv_ram_rwsthp both io registers and output bypass; b), xilinx axi block ram to ddb interface 64bit, 2M capacity; high address bit ignor e c), NV_NVDLA_apb2csb as bridge between selfdefined apb master and csb; C, global defined: DISABLE_TESTPOINTS, SYNTHESIS, FPGA, //NV_SYNTHESIS (no real effect, after searched all of vmod output source code) //RAM_INTERFACE(no effect, after replace all nv_rams) VLIB_BYPASS_POWER_CG, FIFOGEN_MASTER_CLK_GATING_DISABLED, RAM_DISABLE_POWER_GATING_FPGA D, interface config a), dla_core_clk and dla_csb_clk, same clock; b), global_clk_ovr_on, tmc2slcg_disable_clock_gating, test_mode, constant 1'B0; c), dla_reset_rstn, directreset, same low level reset.

2, working phenomenon
    A, so many "X" signal, when write all csb code, nothing happened.
    B, add initial code for no reset inner register, it seems so well.
        trace test "cdp_8x8x32_lrn3_int8_1"
        after csb write(addr:c008, value:0000_0001), ddb axi read datas, from 0000_0000 to 0000_0440,
        after axi block ram response, nvdla no other action.

In fpga implement all above same.

[xivisi]

my initial code just like this: file: NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v line:633 reg [33:0] ram_ff0; initial ram_ff0 = 34'H0;

[xivisi]

It be found out. block ram define error. close