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RTL, Cmodel, and testbench for NVDLA
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CMOD: assertion for certain SDP throughput settings. #223

Open ghost opened 5 years ago

ghost commented 5 years ago

sdp_hls_wrapper.cpp:188 assertion occurs for specs where none of SDP throughput settings is at least x4.

assert(SDP_PARALLEL_PROC_NUM%SPEED_Y == 0);

Where SDP_PARALLEL_PROC_NUM evaluates to MAX3(NVDLA_SDP_BS_THROUGHPUT, NVDLA_SDP_BN_THROUGHPUT, NVDLA_SDP_EW_THROUGHPUT) and SPEED_Y evaluates to fixed constant 4.

I have no idea what SPEED_Y is for, but changing it to 1 at sdp.h:158 fixes the problem (and simulation run with nv_small traces seems to still generate correct output).

anakin1028 commented 5 years ago

@mmaciag I got the exactly same problem when I run the sdp with LUT test case. I think SPEED_Y is the throughput of EW component as defined in spec/defs/nv_large.spec

I guess the assertion is based on the nv_large. In NV_large the X1(BS)/X2(BN) components both have throughput 16 and Y(EW) component has throughput: 4, so MAX of the three is multiple of 4.

Also I guess this assertion should be modified based on the configuration?

anakin1028 commented 5 years ago

@mmaciag after I modified SPEED_Y to 1, the test case: sdp_3x3x33_ew_le_exp_int8 can be run, but the result is FAIL. Can you run this h/w test case successfully?

To run this case I have also enabled the EW/LUT components in nv_small.spec also changes the DMA_READ_CLIENTS from 7 to 8.