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RTL, Cmodel, and testbench for NVDLA
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bug: NV_NVDLA_CDMA_wt.wt_wr_dmatx_cnt, clock is gated when decrease #235

Open kouzhentao opened 5 years ago

kouzhentao commented 5 years ago

Hi

This dmatx_cnt increase when cbuf_wr, decrease when cbuf release. The clock is okay when increase, but is gated when decrease. This will result in a cbuf bank overflow when running nv multi times during inference. Can u please have a look? thx.

Kou

cainiaowu commented 5 years ago

Duplicate of #183