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RTL, Cmodel, and testbench for NVDLA
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Question for PDP Max Pooling #242

Open anakin1028 opened 5 years ago

anakin1028 commented 5 years ago

Hi all,

I have run the test case: pdp_28x28x8_2x2_max_int8_0. But I cannot figure out how the H/W derive the pooling results. The test case input is like the following figure: How does the following memory input organize as a data cube(WxHxC)? I have read the H/W units document, but I cannot connect this memory input with the documentation though...

pooling_input

And how to generate the following output sequence as circled by the red rectangle? b3 ee 5c ba f2 66 4a 8d

pooling_output

Thanks in advance!

fanqifei commented 5 years ago

Hi @anakin1028 , you can take a look at http://nvdla.org/hw/format.html#feature-data-format on the mapping between 3D cube and memory layout.