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nvdla / hw

RTL, Cmodel, and testbench for NVDLA
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why PDP has seven padding value ? #268

Open zhouweiscut opened 5 years ago

zhouweiscut commented 5 years ago

According to PDP hardware doc, there are seven padding value. but CSC has just one padding value. for my understanding, for the same layer, it need just one padding value, but why PDP (pooling) need seven value ? Could anyone give some hints ? thanks!

zhouweiscut commented 5 years ago

Could anyone provide any help ?