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RTL, Cmodel, and testbench for NVDLA
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nv small with *_DATA_TYPE_INT16_FP16 Error #270

Open nsherer opened 5 years ago

nsherer commented 5 years ago

Hi,

Trying to generate an nv_small design with both:

define FEATURE_DATA_TYPE_INT16_FP16

define WEIGHT_DATA_TYPE_INT16_FP16

but receiving the below error:

ERROR: eperl: eval: my $i; for($i = 0; $i < 32; $i ++) { $b0 = 16 $i; $b1 = 16 $i + 15; print "assign wt_nan_mask[${b1}:${b0}] = {16{~wt_fp16_nan_flag_w[${i}]}};\n"; } print "\n\n";

error: Global symbol "$b0" requires explicit package name at (eval 41) line 3, line 994. Global symbol "$b1" requires explicit package name at (eval 41) line 4, line 994. Global symbol "$b1" requires explicit package name at (eval 41) line 5, line 994. Global symbol "$b0" requires explicit package name at (eval 41) line 5, line 994.

at ../../../tools/bin/eperl line 265 eperl_main::Error('eval:\x{a}my $i;\x{a}for($i = 0; $i < 32; $i ++) {\x{a}$b0 = 16 $i;\x{a}$b1...') called at ../../../tools/bin/eperl line 210 eperl_main::EvalScript('my $i;\x{a}for($i = 0; $i < 32; $i ++) {\x{a}$b0 = 16 $i;\x{a}$b1 = 16 ...') called at ../../../tools/bin/eperl line 189 eperl_main::ProcessInput('../../../outdir/nv_small/vmod/nvdla/cdma/NV_NVDLA_CDMA_wt.v.vcp', '../../../outdir/nv_small/vmod/nvdla/cdma/NV_NVDLA_CDMA_wt.v.v...') called at ../../../tools/bin/eperl line 158 make: *** [../../../outdir/nv_small/vmod/nvdla/cdma/NV_NVDLA_CDMA_wt.v] Error 25 Died at ./tools/bin/tmake line 254.


Why is that?

huangwei858 commented 5 years ago

You have to check eperl script settings about your error. nv_small should be set as correct settings or modify reference perl script base on you requirements.

nsherer commented 5 years ago

Can you please provide such script. we would like to have the below confs, please try to compile it and let me know where am I wrong, Should be very simple - only enlarged the width of the DATA/WT to 16 bits

Thx

our spec/defs/nv_small.spec is as below:

//#define NV_SMALL 1

define FEATURE_DATA_TYPE_INT16_FP16

define WEIGHT_DATA_TYPE_INT16_FP16

define WEIGHT_COMPRESSION_DISABLE

define WINOGRAD_DISABLE

define BATCH_DISABLE

define SECONDARY_MEMIF_DISABLE

define SDP_LUT_DISABLE

define SDP_BS_ENABLE

define SDP_BN_ENABLE

define SDP_EW_DISABLE

define BDMA_DISABLE

define RUBIK_DISABLE

define RUBIK_CONTRACT_DISABLE

define RUBIK_RESHAPE_DISABLE

define PDP_ENABLE

define CDP_ENABLE

define RETIMING_DISABLE

define MAC_ATOMIC_C_SIZE_8

define MAC_ATOMIC_K_SIZE_8

define MEMORY_ATOMIC_SIZE_8

define MAX_BATCH_SIZE_x

define CBUF_BANK_NUMBER_32

define CBUF_BANK_WIDTH_8

define CBUF_BANK_DEPTH_512

define SDP_BS_THROUGHPUT_1

define SDP_BN_THROUGHPUT_1

define SDP_EW_THROUGHPUT_x

define PDP_THROUGHPUT_1

define CDP_THROUGHPUT_1

define PRIMARY_MEMIF_LATENCY_50

define SECONDARY_MEMIF_LATENCY_x

//#define PRIMARY_MEMIF_MAX_BURST_LENGTH_4

define PRIMARY_MEMIF_MAX_BURST_LENGTH_1

define PRIMARY_MEMIF_WIDTH_64

define SECONDARY_MEMIF_MAX_BURST_LENGTH_x

define SECONDARY_MEMIF_WIDTH_512

define MEM_ADDRESS_WIDTH_32

define NUM_DMA_READ_CLIENTS_7

define NUM_DMA_WRITE_CLIENTS_3

include "projects.spec"

shazib-summar commented 4 years ago

Doesn't nv_small only support INT8 configuration?

nsherer commented 4 years ago

Hi,

We overcame that issue. modified the small to support also INT16.

Thanks anyway, Neta

Neta Sherer

M: +972 54 7916089 <%2B972%2054%202522023> | T: +972 77 2518840 <%2B972%2077%202518844>

E: neta.sherer@adasky.com | www.adasky.com http://www.adasky.com/

On Thu, Sep 19, 2019 at 8:44 AM Shazib Summar Roy notifications@github.com wrote:

Doesn't nv_small only support INT8 configuration?

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shazib-summar commented 4 years ago

How, if I may ask?

nsherer commented 4 years ago

Just used the supplied scripts and modified it accordingly.

shazib-summar commented 4 years ago

Bro, I'm working on a different project now. Thanks for replying though.

LeiWang1999 commented 3 years ago

Hi, @nsherer What the branch did you use ? I notice that the master branch project.spec can only support int8 feature/weight datatype rtl generate. But the nvdlav1 branch can not generate fpga ram dir.