build verilator error - Githubissues

Hi, I have this problem build verilator with master branch nv_small

i had many error but solved like this https://github.com/nvdla/hw/issues/146#issuecomment-404773479 But as a result, I failed.

How can i solve this problem?

%Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_mcif.v:265: Cell has missing pin: reg2dp_rd_weight_bdma %Warning-PINMISSING: Use "/ verilator lint_off PINMISSING /" and lint_on around source to disable this message. %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_mcif.v:265: Cell has missing pin: reg2dp_rd_weight_rbk %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_mcif.v:265: Cell has missing pin: reg2dp_rd_weight_sdp_e %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_mcif.v:265: Cell has missing pin: reg2dp_wr_weight_bdma %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_mcif.v:265: Cell has missing pin: reg2dp_wr_weight_rbk %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: dp2reg_lut_hybrid %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: dp2reg_lut_int_data %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: dp2reg_lut_le_hit %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: dp2reg_lut_lo_hit %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: dp2reg_lut_oflow %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: dp2reg_lut_uflow %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_ew_alu_algo %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_ew_alu_bypass %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_ew_alu_cvt_bypass %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_ew_alu_cvt_offset %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_ew_alu_cvt_scale %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_ew_alu_cvt_truncate %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_ew_alu_operand %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_ew_alu_src %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_ew_bypass %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_ew_lut_bypass %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_ew_mul_bypass %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_ew_mul_cvt_bypass %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_ew_mul_cvt_offset %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_ew_mul_cvt_scale %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_ew_mul_cvt_truncate %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_ew_mul_operand %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_ew_mul_prelu %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_ew_mul_src %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_ew_truncate %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_lut_hybrid_priority %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_lut_int_access_type %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_lut_int_addr %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_lut_int_data %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_lut_int_data_wr %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_lut_int_table_id %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_lut_le_end %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_lut_le_function %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_lut_le_index_offset %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_lut_le_index_select %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_lut_le_slope_oflow_scale %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_lut_le_slope_oflow_shift %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_lut_le_slope_uflow_scale %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_lut_le_slope_uflow_shift %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_lut_le_start %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_lut_lo_end %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_lut_lo_index_select %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_lut_lo_slope_oflow_scale %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_lut_lo_slope_oflow_shift %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_lut_lo_slope_uflow_scale %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_lut_lo_slope_uflow_shift %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_lut_lo_start %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_lut_oflow_priority %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_lut_slcg_en %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_sdp.v:365: Cell has missing pin: reg2dp_lut_uflow_priority %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/glb/NV_NVDLA_GLB_csb.v:200: Cell has missing pin: bdma_done_mask0 %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/glb/NV_NVDLA_GLB_csb.v:200: Cell has missing pin: bdma_done_mask1 %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/glb/NV_NVDLA_GLB_csb.v:200: Cell has missing pin: rubik_done_mask0 %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/glb/NV_NVDLA_GLB_csb.v:200: Cell has missing pin: rubik_done_mask1 %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_rdma.v:351: Cell has missing pin: reg2dp_erdma_data_mode %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_rdma.v:351: Cell has missing pin: reg2dp_erdma_data_size %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_rdma.v:351: Cell has missing pin: reg2dp_erdma_data_use %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_rdma.v:351: Cell has missing pin: reg2dp_erdma_disable %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_rdma.v:351: Cell has missing pin: reg2dp_erdma_ram_type %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_rdma.v:351: Cell has missing pin: reg2dp_ew_base_addr_high %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_rdma.v:351: Cell has missing pin: reg2dp_ew_base_addr_low %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_rdma.v:351: Cell has missing pin: reg2dp_ew_batch_stride %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_rdma.v:351: Cell has missing pin: reg2dp_ew_line_stride %Warning-PINMISSING: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_rdma.v:351: Cell has missing pin: reg2dp_ew_surface_stride %Warning-IMPLICIT: ../../outdir/nv_small/vmod/vlibs/SDFSNQD1.v:24: Signal definition not found, creating implicitly: sel %Warning-IMPLICIT: ../../outdir/nv_small/vmod/vlibs/SDFCNQD1.v:24: Signal definition not found, creating implicitly: sel %Warning-IMPLICIT: ../../outdir/nv_small/vmod/vlibs/SDFQD1.v:22: Signal definition not found, creating implicitly: sel %Warning-IMPLICIT: ../../outdir/nv_small/vmod/nvdla/top/NV_nvdla.v:334: Signal definition not found, creating implicitly: nvdla_core2cvsram_aw_awvalid %Warning-IMPLICIT: ../../outdir/nv_small/vmod/nvdla/top/NV_nvdla.v:335: Signal definition not found, creating implicitly: nvdla_core2cvsram_w_wvalid %Warning-IMPLICIT: ../../outdir/nv_small/vmod/nvdla/top/NV_nvdla.v:336: Signal definition not found, creating implicitly: nvdla_core2cvsram_w_wlast %Warning-IMPLICIT: ../../outdir/nv_small/vmod/nvdla/top/NV_nvdla.v:337: Signal definition not found, creating implicitly: nvdla_core2cvsram_b_bready %Warning-IMPLICIT: ../../outdir/nv_small/vmod/nvdla/top/NV_nvdla.v:338: Signal definition not found, creating implicitly: nvdla_core2cvsram_r_rready %Warning-WIDTH: ../../outdir/nv_small/vmod/rams/model/RAMPDP_80X17_GL_M2_D2.v:1082: Bit extraction of array[39:0] requires 6 bit index, not 7 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/rams/model/RAMPDP_80X17_GL_M2_D2.v:1130: Bit extraction of array[39:0] requires 6 bit index, not 7 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/rams/model/RAMPDP_128X18_GL_M2_D2.v:1134: Bit extraction of array[63:0] requires 6 bit index, not 7 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/rams/model/RAMPDP_128X18_GL_M2_D2.v:1182: Bit extraction of array[63:0] requires 6 bit index, not 7 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_unpack.v:83: Operator COND expects 4 bits on the Conditional False, but Conditional False's VARREF 'pack_cnt_nxt' generates 3 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_unpack.v:102: Operator EQ expects 3 bits on the LHS, but LHS's VARREF 'pack_cnt' generates 2 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_unpack.v:103: Operator EQ expects 3 bits on the LHS, but LHS's VARREF 'pack_cnt' generates 2 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_unpack.v:104: Operator EQ expects 3 bits on the LHS, but LHS's VARREF 'pack_cnt' generates 2 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_unpack.v:105: Operator EQ expects 3 bits on the LHS, but LHS's VARREF 'pack_cnt' generates 2 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/vlibs/NV_NVDLA_HLS_shiftrightsatsu.v:44: Operator ADD expects 18 bits on the RHS, but RHS's VARREF 'point5' generates 1 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_EG_din.v:125: Operator ADD expects 3 bits on the LHS, but LHS's SEL generates 1 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_EG_din.v:125: Operator ADD expects 3 bits on the RHS, but RHS's SEL generates 1 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_EG_din.v:131: Operator ADD expects 14 bits on the RHS, but RHS's VARREF 'lat_ecc_rd_size' generates 3 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/vlibs/NV_NVDLA_HLS_shiftrightsu.v:42: Operator ADD expects 18 bits on the RHS, but RHS's VARREF 'point5' generates 1 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/vlibs/NV_NVDLA_HLS_shiftrightsu.v:42: Operator ADD expects 10 bits on the RHS, but RHS's VARREF 'point5' generates 1 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/vlibs/NV_NVDLA_HLS_shiftrightsu.v:47: Operator GTE expects 32 bits on the LHS, but LHS's VARREF 'shift_num' generates 5 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/vlibs/NV_NVDLA_HLS_shiftrightsu.v:42: Operator ADD expects 9 bits on the RHS, but RHS's VARREF 'point5' generates 1 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/vlibs/NV_NVDLA_HLS_shiftrightsu.v:47: Operator GTE expects 32 bits on the LHS, but LHS's VARREF 'shift_num' generates 6 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/vlibs/NV_NVDLA_HLS_shiftrightsu.v:42: Operator ADD expects 33 bits on the RHS, but RHS's VARREF 'point5' generates 1 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_DAT_out.v:480: Operator ADD expects 14 bits on the RHS, but RHS's VARREF 'size_of_atom' generates 3 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_DAT_out.v:495: Operator SUB expects 15 bits on the RHS, but RHS's VARREF 'beat_count' generates 13 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_DAT_out.v:528: Operator COND expects 4 bits on the Conditional False, but Conditional False's VARREF 'dfifo_rd_size' generates 3 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_REG_dual.v:352: Operator CASE expects 32 bits on the Case expression, but Case expression's VARREF 'reg_offset_rd_int' generates 12 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_REG_dual.v:710: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's TESTPLUSARGS 'arreggen_dump_wr' generates 32 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_REG_dual.v:711: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's TESTPLUSARGS 'arreggen_abort_on_rowr' generates 32 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_REG_dual.v:712: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's TESTPLUSARGS 'arreggen_abort_on_invalid_wr' generates 32 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_REG_dual.v:720: Operator CASE expects 32 bits on the Case expression, but Case expression's VARREF 'reg_offset' generates 12 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_REG_single.v:66: Operator CASE expects 32 bits on the Case expression, but Case expression's VARREF 'reg_offset_rd_int' generates 12 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_REG_single.v:96: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's TESTPLUSARGS 'arreggen_dump_wr' generates 32 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_REG_single.v:97: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's TESTPLUSARGS 'arreggen_abort_on_rowr' generates 32 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_REG_single.v:98: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's TESTPLUSARGS 'arreggen_abort_on_invalid_wr' generates 32 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_REG_single.v:106: Operator CASE expects 32 bits on the Case expression, but Case expression's VARREF 'reg_offset' generates 12 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_eg.v:151: Operator ADD expects 3 bits on the LHS, but LHS's SEL generates 1 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_eg.v:151: Operator ADD expects 3 bits on the RHS, but RHS's SEL generates 1 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_eg.v:159: Operator ADD expects 16 bits on the RHS, but RHS's VARREF 'lat_fifo_rd_size' generates 3 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_eg.v:364: Operator ADD expects 3 bits on the LHS, but LHS's SEL generates 1 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_eg.v:364: Operator ADD expects 3 bits on the RHS, but RHS's SEL generates 1 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_eg.v:365: Operator ADD expects 3 bits on the LHS, but LHS's SEL generates 1 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_eg.v:365: Operator ADD expects 3 bits on the RHS, but RHS's SEL generates 1 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_ig.v:386: Operator SHIFTL expects 32 or 15 bits on the LHS, but LHS's VARREF 'reg2dp_width' generates 13 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_ig.v:388: Operator SHIFTL expects 32 or 15 bits on the LHS, but LHS's VARREF 'reg2dp_width' generates 13 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_ig.v:394: Operator SHIFTL expects 32 or 15 bits on the LHS, but LHS's VARREF 'reg2dp_width' generates 13 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_ig.v:399: Operator SHIFTL expects 32 or 15 bits on the LHS, but LHS's VARREF 'reg2dp_width' generates 13 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_ig.v:426: Operator SHIFTL expects 32 or 15 bits on the LHS, but LHS's VARREF 'size_of_surf' generates 11 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_ig.v:428: Operator SHIFTL expects 32 or 15 bits on the LHS, but LHS's VARREF 'size_of_surf' generates 11 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_ig.v:432: Operator SHIFTL expects 32 or 15 bits on the LHS, but LHS's VARREF 'size_of_surf' generates 11 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_ig.v:434: Operator SHIFTL expects 32 or 15 bits on the LHS, but LHS's VARREF 'size_of_surf' generates 11 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_ig.v:440: Operator SHIFTL expects 32 or 15 bits on the LHS, but LHS's VARREF 'size_of_surf' generates 11 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_ig.v:442: Operator SHIFTL expects 32 or 15 bits on the LHS, but LHS's VARREF 'size_of_surf' generates 11 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_ig.v:446: Operator SHIFTL expects 32 or 15 bits on the LHS, but LHS's VARREF 'size_of_surf' generates 11 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_ig.v:448: Operator SHIFTL expects 32 or 15 bits on the LHS, but LHS's VARREF 'size_of_surf' generates 11 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_ig.v:597: Operator ADD expects 34 bits on the LHS, but LHS's VARREF 'stl_cnt_cur' generates 32 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_ig.v:598: Operator SUB expects 34 bits on the LHS, but LHS's VARREF 'stl_cnt_cur' generates 32 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_ig.v:546: Operator ADD expects 34 bits on the LHS, but LHS's VARREF 'stl_cnt_cur' generates 32 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_MRDMA_ig.v:547: Operator SUB expects 34 bits on the LHS, but LHS's VARREF 'stl_cnt_cur' generates 32 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_REG_dual.v:185: Operator CASE expects 32 bits on the Case expression, but Case expression's VARREF 'reg_offset_rd_int' generates 12 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_REG_dual.v:352: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's TESTPLUSARGS 'arreggen_dump_wr' generates 32 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_REG_dual.v:353: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's TESTPLUSARGS 'arreggen_abort_on_rowr' generates 32 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_REG_dual.v:354: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's TESTPLUSARGS 'arreggen_abort_on_invalid_wr' generates 32 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_REG_dual.v:362: Operator CASE expects 32 bits on the Case expression, but Case expression's VARREF 'reg_offset' generates 12 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_REG_single.v:66: Operator CASE expects 32 bits on the Case expression, but Case expression's VARREF 'reg_offset_rd_int' generates 12 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_REG_single.v:96: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's TESTPLUSARGS 'arreggen_dump_wr' generates 32 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_REG_single.v:97: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's TESTPLUSARGS 'arreggen_abort_on_rowr' generates 32 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_REG_single.v:98: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's TESTPLUSARGS 'arreggen_abort_on_invalid_wr' generates 32 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_REG_single.v:106: Operator CASE expects 32 bits on the Case expression, but Case expression's VARREF 'reg_offset' generates 12 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_LUT_CTRL_unit.v:484: Operator COND expects 32 or 6 bits on the Conditional False, but Conditional False's SEL generates 5 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/cdp/int_sum_block_tp1.v:125: Operator ADD expects 20 bits on the LHS, but LHS's VARREF 'int8_sum_3_5' generates 18 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/cdp/int_sum_block_tp1.v:125: Operator ADD expects 20 bits on the RHS, but RHS's REPLICATE generates 18 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/cdp/int_sum_block_tp1.v:132: Operator ADD expects 20 bits on the LHS, but LHS's VARREF 'int8_sum_3_5' generates 18 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/cdp/int_sum_block_tp1.v:132: Operator ADD expects 20 bits on the RHS, but RHS's REPLICATE generates 18 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/cdp/int_sum_block_tp1.v:132: Operator ADD expects 20 bits on the LHS, but LHS's VARREF 'int8_sum_2_6' generates 18 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/cdp/int_sum_block_tp1.v:132: Operator ADD expects 20 bits on the RHS, but RHS's VARREF 'int8_sum_1_7' generates 18 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/cdp/int_sum_block_tp1.v:139: Operator ADD expects 21 bits on the LHS, but LHS's VARREF 'int8_sum_3_5' generates 18 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/cdp/int_sum_block_tp1.v:139: Operator ADD expects 21 bits on the RHS, but RHS's REPLICATE generates 18 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/cdp/int_sum_block_tp1.v:139: Operator ADD expects 21 bits on the LHS, but LHS's VARREF 'int8_sum_2_6' generates 18 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/cdp/int_sum_block_tp1.v:139: Operator ADD expects 21 bits on the RHS, but RHS's VARREF 'int8_sum_1_7' generates 18 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_REG_dual.v:153: Operator CASE expects 32 bits on the Case expression, but Case expression's VARREF 'reg_offset_rd_int' generates 12 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_REG_dual.v:273: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's TESTPLUSARGS 'arreggen_dump_wr' generates 32 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_REG_dual.v:274: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's TESTPLUSARGS 'arreggen_abort_on_rowr' generates 32 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_REG_dual.v:275: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's TESTPLUSARGS 'arreggen_abort_on_invalid_wr' generates 32 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_REG_dual.v:283: Operator CASE expects 32 bits on the Case expression, but Case expression's VARREF 'reg_offset' generates 12 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_REG_single.v:66: Operator CASE expects 32 bits on the Case expression, but Case expression's VARREF 'reg_offset_rd_int' generates 12 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_REG_single.v:96: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's TESTPLUSARGS 'arreggen_dump_wr' generates 32 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_REG_single.v:97: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's TESTPLUSARGS 'arreggen_abort_on_rowr' generates 32 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_REG_single.v:98: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's TESTPLUSARGS 'arreggen_abort_on_invalid_wr' generates 32 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_REG_single.v:106: Operator CASE expects 32 bits on the Case expression, but Case expression's VARREF 'reg_offset' generates 12 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_WRITE_IG_cvt.v:221: Operator ASSIGNDLY expects 2 bits on the Assign RHS, but Assign RHS's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_WRITE_IG_cvt.v:274: Operator ADD expects 10 bits on the RHS, but RHS's VARREF 'os_inp_add_nxt' generates 3 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_WRITE_IG_cvt.v:274: Operator SUB expects 10 bits on the RHS, but RHS's VARREF 'os_inp_sub_nxt' generates 3 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_WRITE_IG_cvt.v:300: Operator ADD expects 11 bits on the LHS, but LHS's VARREF 'os_cnt_cur' generates 9 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_WRITE_IG_cvt.v:300: Operator ADD expects 11 bits on the RHS, but RHS's SEL generates 3 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_WRITE_IG_cvt.v:300: Operator SUB expects 11 bits on the RHS, but RHS's SEL generates 3 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_WRITE_IG_arb.v:318: Operator ASSIGNW expects 45 bits on the Assign RHS, but Assign RHS's CONST '1'h0' generates 1 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_WRITE_IG_arb.v:319: Operator ASSIGNW expects 65 bits on the Assign RHS, but Assign RHS's CONST '1'h0' generates 1 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_WRITE_IG_arb.v:322: Operator ASSIGNW expects 45 bits on the Assign RHS, but Assign RHS's CONST '1'h0' generates 1 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_WRITE_IG_arb.v:323: Operator ASSIGNW expects 65 bits on the Assign RHS, but Assign RHS's CONST '1'h0' generates 1 bits. %Warning-LITENDIAN: ../../outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_WRITE_IG_bpt.v:83: Little bit endian vector: MSB < LSB of bit range: -1:0 %Warning-LITENDIAN: ../../outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_WRITE_IG_bpt.v:84: Little bit endian vector: MSB < LSB of bit range: -1:0 %Warning-LITENDIAN: ../../outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_WRITE_IG_bpt.v:85: Little bit endian vector: MSB < LSB of bit range: -1:0 %Warning-LITENDIAN: ../../outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_WRITE_IG_bpt.v:86: Little bit endian vector: MSB < LSB of bit range: -1:0 %Warning-LITENDIAN: ../../outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_WRITE_IG_bpt.v:87: Little bit endian vector: MSB < LSB of bit range: -1:0 %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_WRITE_IG_bpt.v:243: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS's REPLICATE generates 2 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_WRITE_IG_bpt.v:266: Operator ADD expects 32 bits on the LHS, but LHS's VARREF 'ftran_size' generates 3 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_READ_IG_cvt.v:102: Operator ADD expects 10 bits on the RHS, but RHS's VARREF 'os_inp_add_nxt' generates 3 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_READ_IG_cvt.v:102: Operator SUB expects 10 bits on the RHS, but RHS's VARREF 'os_inp_sub_nxt' generates 1 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_READ_IG_cvt.v:127: Operator ADD expects 11 bits on the LHS, but LHS's VARREF 'os_cnt_cur' generates 9 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_READ_IG_cvt.v:127: Operator ADD expects 11 bits on the RHS, but RHS's SEL generates 3 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_READ_IG_cvt.v:127: Operator SUB expects 11 bits on the RHS, but RHS's SEL generates 1 bits. %Warning-LITENDIAN: ../../outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_READ_IG_bpt.v:67: Little bit endian vector: MSB < LSB of bit range: -1:0 %Warning-LITENDIAN: ../../outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_READ_IG_bpt.v:68: Little bit endian vector: MSB < LSB of bit range: -1:0 %Warning-LITENDIAN: ../../outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_READ_IG_bpt.v:69: Little bit endian vector: MSB < LSB of bit range: -1:0 %Warning-LITENDIAN: ../../outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_READ_IG_bpt.v:70: Little bit endian vector: MSB < LSB of bit range: -1:0 %Warning-LITENDIAN: ../../outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_READ_IG_bpt.v:71: Little bit endian vector: MSB < LSB of bit range: -1:0 %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_READ_IG_bpt.v:197: Operator ADD expects 11 bits on the LHS, but LHS's VARREF 'lat_cnt_cur' generates 9 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_READ_IG_bpt.v:197: Operator ADD expects 11 bits on the RHS, but RHS's SEL generates 3 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_READ_IG_bpt.v:197: Operator SUB expects 11 bits on the RHS, but RHS's SEL generates 1 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_REG_dual.v:478: Operator CASE expects 32 bits on the Case expression, but Case expression's VARREF 'reg_offset_rd_int' generates 12 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_REG_dual.v:983: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's TESTPLUSARGS 'arreggen_dump_wr' generates 32 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_REG_dual.v:984: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's TESTPLUSARGS 'arreggen_abort_on_rowr' generates 32 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_REG_dual.v:985: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's TESTPLUSARGS 'arreggen_abort_on_invalid_wr' generates 32 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_REG_dual.v:993: Operator CASE expects 32 bits on the Case expression, but Case expression's VARREF 'reg_offset' generates 12 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_REG_single.v:188: Operator CASE expects 32 bits on the Case expression, but Case expression's VARREF 'reg_offset_rd_int' generates 12 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_REG_single.v:365: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's TESTPLUSARGS 'arreggen_dump_wr' generates 32 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_REG_single.v:366: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's TESTPLUSARGS 'arreggen_abort_on_rowr' generates 32 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_REG_single.v:367: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's TESTPLUSARGS 'arreggen_abort_on_invalid_wr' generates 32 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_REG_single.v:375: Operator CASE expects 32 bits on the Case expression, but Case expression's VARREF 'reg_offset' generates 12 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_unpack.v:77: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'pack_cnt' generates 4 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_pack.v:65: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'pack_cnt' generates 4 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_RDMA_pack.v:78: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'pack_cnt' generates 4 bits. %Warning-WIDTH: ../../outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_WDMA_intr.v:271: Operator ADD expects 34 bits on the LHS, but LHS's VARREF 'stl_cnt_cur' generates 32 bits. [TMAKE]: nv_small: FAIL

nvdla / hw

build verilator error #284