nvdla / hw

RTL, Cmodel, and testbench for NVDLA
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verification error #287

Closed jyj-yj closed 5 years ago

jyj-yj commented 5 years ago

I'm following this guide and I found a error.

esa@hush34:~/jyj/nvdla_2/hw$ mkdir health_exam
esa@hush34:~/jyj/nvdla_2/hw$ cd health_exam
esa@hush34:~/jyj/nvdla_2/hw/health_exam$ ../verif/tools/run_test.py -P nv_small dc_24x33x55_5x5x55x25_int8_0 -outdir dc_24x33x55_5x5x55x25_int8_output -wave -v nvdla_utb
Traceback (most recent call last):
  File "../verif/tools/run_test.py", line 11, in <module>
    import nvdla_tb_sim_cfg
  File "/home/esa/jyj/nvdla_2/hw/verif/tools/nvdla_tb_sim_cfg.py", line 221
    SB_CFG = { **CDMA_SB_CFG,
                ^
SyntaxError: invalid syntax
esa@hush34:~/jyj/nvdla_2/hw/health_exam$

My tree.make is as follows. Can someone help me?

## ================================================================
## NVDLA Open Source Project
##
## Copyright(c) 2016 - 2017 NVIDIA Corporation.  Licensed under the
## NVDLA Open Hardware License; Check LICENSE which comes with
## this distribution for more information.
## ================================================================

##=======================                                                           
## Project Name Setup, multiple projects supported
##=======================                                                           
PROJECTS := nv_small
                                                                                                                                                                        ##=======================                                                           
##Linux Environment Setup                                                           
##=======================                                                           
                                                                                                                                                                        USE_DESIGNWARE  := 0
DESIGNWARE_DIR  := /home/tools/synopsys/syn_2011.09/dw/sim_ver
CPP  := /usr/bin/cpp
GCC  := /usr/bin/gcc
CXX  := /usr/bin/g++
PERL := /usr/bin/perl
JAVA := /usr/bin/java
SYSTEMC := /home/ip/shared/inf/SystemC/1.0/20151112/systemc-2.3.0/GCC472_64_DBG
PYTHON := /usr/bin/python
VCS_HOME := /home/tools/vcs/mx-2016.06-SP2-4
NOVAS_HOME := /home/tools/debussy/verdi3_2016.06-SP2-9
VERDI_HOME := /home/tools/debussy/verdi3_2016.06-SP2-9
VERILATOR := verilator
CLANG := /home/utils/llvm-4.0.1/bin/clang
~