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RTL, Cmodel, and testbench for NVDLA
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sim_vivado for v2? #291

Closed jyj-yj closed 5 years ago

jyj-yj commented 5 years ago

I tried to verify a nvdla project by following this guide. I have a trouble in verifying since no synopsys vcs in my environment. BTW, I found 'hw/verif/sim_vivado/' in nvdla1 branch. I checked files in 'hw/verif/dut/' of nvdla1, and found that those are for nvdla v1. I manually changed those contents of files according to nvdla v2 and run 'make build', but I got this error. Just see last few lines w/ lut_in_oflow0 errors.

esa@hush34:~/jyj/nvdla_2/hw/verif/sim_vivado$ make build
DUTDIR = dut
VIPDIR = vip
Using cleartext directories
/opt/Xilinx/Vivado/2018.2//bin/xvlog timescale.v -f /home/esa/jyj/nvdla_2/hw/verif/dut/dut.vivado.f   --sourcelibdir /home/esa/jyj/nvdla_2/hw/verif/synth_tb --sourcelibdir /home/esa/jyj/nvdla_2/hw/verif/../outdir/nv_small/vmod/vlibs -include /home/esa/jyj/nvdla_2/hw/verif/synth_tb -include /home/esa/jyj/nvdla_2/hw/verif/dut -sourcelibdir /home/esa/jyj/nvdla_2/hw/verif/../outdir/nv_small/vmod/vlibs -include /home/esa/jyj/nvdla_2/hw/verif/../outdir/nv_small/vmod/include -include /home/esa/jyj/nvdla_2/hw/verif/../outdir/nv_small/vmod/vlibs -include ..  -d DESIGNWARE_NOEXIST -d VIVADO -d NVTOOLS_SYNC2D_GENERIC_CELL -d NO_PERFMON_HISTOGRAM -d PRAND_OFF -sv  /home/esa/jyj/nvdla_2/hw/verif/synth_tb/csb_master.v /home/esa/jyj/nvdla_2/hw/verif/synth_tb/csb_master_seq.v /home/esa/jyj/nvdla_2/hw/verif/synth_tb/axi_slave.v /home/esa/jyj/nvdla_2/hw/verif/synth_tb/id_fifo.v /home/esa/jyj/nvdla_2/hw/verif/synth_tb/memory.v /home/esa/jyj/nvdla_2/hw/verif/synth_tb/memresp_fifo.v /home/esa/jyj/nvdla_2/hw/verif/synth_tb/raddr_fifo.v /home/esa/jyj/nvdla_2/hw/verif/synth_tb/slave_mem_wrap.v /home/esa/jyj/nvdla_2/hw/verif/synth_tb/waddr_fifo.v /home/esa/jyj/nvdla_2/hw/verif/synth_tb/wdata_fifo.v /home/esa/jyj/nvdla_2/hw/verif/synth_tb/wstrb_fifo.v /home/esa/jyj/nvdla_2/hw/verif/synth_tb/clk_divider.v /home/esa/jyj/nvdla_2/hw/verif/synth_tb/slave2mem_rd.v /home/esa/jyj/nvdla_2/hw/verif/synth_tb/slave2mem_wr.v /home/esa/jyj/nvdla_2/hw/verif/../outdir/nv_small/vmod/vlibs/NV_DW02_tree.v /home/esa/jyj/nvdla_2/hw/verif/../outdir/nv_small/vmod/vlibs/NV_DW_lsd.v /home/esa/jyj/nvdla_2/hw/verif/../outdir/nv_small/vmod/vlibs/NV_DW_minmax.v /home/esa/jyj/nvdla_2/hw/verif/synth_tb/tb_top.v -L xsim.compile.log ; /opt/Xilinx/Vivado/2018.2//bin/xelab top --debug all
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/verif/sim_vivado/timescale.v" into library work
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/bdma/NV_NVDLA_BDMA_cq.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_BDMA_cq
INFO: [VRFC 10-311] analyzing module NV_NVDLA_BDMA_cq_flopram_rwsa_20x161
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/bdma/NV_NVDLA_BDMA_csb.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_BDMA_csb
INFO: [VRFC 10-311] analyzing module NV_NVDLA_BDMA_LOAD_csb_fifo
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/bdma/NV_NVDLA_BDMA_gate.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_BDMA_gate
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/bdma/NV_NVDLA_BDMA_load.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_BDMA_load
INFO: [VRFC 10-311] analyzing module NV_NVDLA_BDMA_LOAD_pipe_p1
INFO: [VRFC 10-311] analyzing module NV_NVDLA_BDMA_LOAD_pipe_p2
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/bdma/NV_NVDLA_BDMA_reg.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_BDMA_reg
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/bdma/NV_NVDLA_BDMA_store.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_BDMA_store
INFO: [VRFC 10-311] analyzing module NV_NVDLA_BDMA_STORE_pipe_p1
INFO: [VRFC 10-311] analyzing module NV_NVDLA_BDMA_STORE_pipe_p3
INFO: [VRFC 10-311] analyzing module NV_NVDLA_BDMA_STORE_lat_fifo
INFO: [VRFC 10-311] analyzing module NV_NVDLA_BDMA_STORE_fifo_r2w
INFO: [VRFC 10-311] analyzing module NV_NVDLA_BDMA_STORE_fifo_r2w_flopram_rwsa_4x514
INFO: [VRFC 10-311] analyzing module NV_NVDLA_BDMA_STORE_fifo_intr
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/bdma/NV_NVDLA_bdma.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_bdma
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_buffer.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CACC_assembly_buffer
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cacc/NV_NVDLA_CACC_assembly_ctrl.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CACC_assembly_ctrl
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cacc/NV_NVDLA_CACC_calculator.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CACC_calculator
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cacc/NV_NVDLA_CACC_delivery_buffer.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CACC_delivery_buffer
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cacc/NV_NVDLA_CACC_delivery_ctrl.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CACC_delivery_ctrl
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cacc/NV_NVDLA_CACC_dual_reg.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CACC_dual_reg
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cacc/NV_NVDLA_CACC_regfile.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CACC_regfile
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cacc/NV_NVDLA_CACC_single_reg.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CACC_single_reg
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cacc/NV_NVDLA_CACC_slcg.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CACC_slcg
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cacc/NV_NVDLA_cacc.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_cacc
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/car/NV_NVDLA_core_reset.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_core_reset
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/car/NV_NVDLA_reset.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_reset
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/car/NV_NVDLA_sync3d.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_sync3d
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/car/NV_NVDLA_sync3d_c.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_sync3d_c
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/car/NV_NVDLA_sync3d_s.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_sync3d_s
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cbuf/NV_NVDLA_cbuf.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_cbuf
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdma/NV_NVDLA_CDMA_CVT_cell.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDMA_CVT_cell
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDMA_CVT_CELL_pipe_p1
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDMA_CVT_CELL_pipe_p2
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDMA_CVT_CELL_pipe_p3
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdma/NV_NVDLA_CDMA_DC_fifo.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDMA_DC_fifo
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdma/NV_NVDLA_CDMA_IMG_ctrl.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDMA_IMG_ctrl
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdma/NV_NVDLA_CDMA_IMG_fifo.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDMA_IMG_fifo
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdma/NV_NVDLA_CDMA_IMG_pack.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDMA_IMG_pack
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdma/NV_NVDLA_CDMA_IMG_sg.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDMA_IMG_sg
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdma/NV_NVDLA_CDMA_IMG_sg2pack_fifo.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDMA_IMG_sg2pack_fifo
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDMA_IMG_sg2pack_fifo_flopram_rwsa_128x11
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdma/NV_NVDLA_CDMA_WG_fifo.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDMA_WG_fifo
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDMA_WG_fifo_folded_ram_rws_128x5
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdma/NV_NVDLA_CDMA_WT_fifo.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDMA_WT_fifo
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdma/NV_NVDLA_CDMA_WT_sp_arb.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDMA_WT_sp_arb
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdma/NV_NVDLA_CDMA_WT_wgs_fifo.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDMA_WT_wgs_fifo
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdma/NV_NVDLA_CDMA_WT_wrr_arb.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDMA_WT_wrr_arb
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdma/NV_NVDLA_CDMA_cvt.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDMA_cvt
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdma/NV_NVDLA_CDMA_dc.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDMA_dc
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdma/NV_NVDLA_CDMA_dma_mux.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDMA_dma_mux
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdma/NV_NVDLA_CDMA_dual_reg.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDMA_dual_reg
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdma/NV_NVDLA_CDMA_img.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDMA_img
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdma/NV_NVDLA_CDMA_regfile.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDMA_regfile
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdma/NV_NVDLA_CDMA_shared_buffer.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDMA_shared_buffer
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdma/NV_NVDLA_CDMA_single_reg.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDMA_single_reg
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdma/NV_NVDLA_CDMA_slcg.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDMA_slcg
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdma/NV_NVDLA_CDMA_status.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDMA_status
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdma/NV_NVDLA_CDMA_wg.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDMA_wg
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDMA_WG_pipe_p1
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDMA_WG_pipe_p3
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdma/NV_NVDLA_CDMA_wt.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDMA_wt
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDMA_WT_8ATMM_fifo
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdma/NV_NVDLA_cdma.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_cdma
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_INTP_unit.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDP_DP_INTP_unit
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_LUT_CTRL_unit.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDP_DP_LUT_CTRL_unit
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_LUT_ctrl.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDP_DP_LUT_ctrl
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_MUL_unit.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDP_DP_MUL_unit
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_bufferin.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDP_DP_bufferin
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_cvtin.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDP_DP_cvtin
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDP_DP_CVTIN_pipe_p1
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDP_DP_CVTIN_pipe_p2
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDP_DP_CVTIN_pipe_p3
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_cvtout.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDP_DP_cvtout
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDP_DP_CVTOUT_pipe_p1
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDP_DP_CVTOUT_pipe_p2
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDP_DP_CVTOUT_pipe_p3
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDP_DP_CVTOUT_pipe_p4
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_intp.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDP_DP_intp
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_lut.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDP_DP_lut
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_mul.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDP_DP_mul
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_nan.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDP_DP_nan
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_sum.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDP_DP_sum
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdp/NV_NVDLA_CDP_DP_syncfifo.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDP_DP_syncfifo
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDP_DP_info_fifo
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_REG_dual.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDP_RDMA_REG_dual
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_REG_single.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDP_RDMA_REG_single
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_cq.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDP_RDMA_cq
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDP_RDMA_cq_flopram_rwsa_256x7
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_eg.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDP_RDMA_eg
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_ig.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDP_RDMA_ig
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdp/NV_NVDLA_CDP_RDMA_reg.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDP_RDMA_reg
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdp/NV_NVDLA_CDP_REG_dual.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDP_REG_dual
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdp/NV_NVDLA_CDP_REG_single.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDP_REG_single
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdp/NV_NVDLA_CDP_dp.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDP_dp
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdp/NV_NVDLA_CDP_rdma.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDP_rdma
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdp/NV_NVDLA_CDP_reg.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDP_reg
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdp/NV_NVDLA_CDP_slcg.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDP_slcg
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdp/NV_NVDLA_CDP_wdma.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDP_wdma
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDP_WDMA_cmd_fifo
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDP_WDMA_cmd_fifo_flopram_rwsa_4x17
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CDP_WDMA_intr_fifo
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdp/NV_NVDLA_cdp.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_cdp
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdp/fp_format_cvt.v" into library work
INFO: [VRFC 10-311] analyzing module fp_format_cvt
INFO: [VRFC 10-311] analyzing module FP_FORMAT_CVT_pipe_p1
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdp/fp_sum_block.v" into library work
INFO: [VRFC 10-311] analyzing module fp_sum_block
INFO: [VRFC 10-311] analyzing module FP_SUM_BLOCK_pipe_p1
INFO: [VRFC 10-311] analyzing module FP_SUM_BLOCK_pipe_p2
INFO: [VRFC 10-311] analyzing module FP_SUM_BLOCK_pipe_p3
INFO: [VRFC 10-311] analyzing module FP_SUM_BLOCK_pipe_p4
INFO: [VRFC 10-311] analyzing module FP_SUM_BLOCK_pipe_p5
INFO: [VRFC 10-311] analyzing module FP_SUM_BLOCK_pipe_p6
INFO: [VRFC 10-311] analyzing module FP_SUM_BLOCK_pipe_p7
INFO: [VRFC 10-311] analyzing module FP_SUM_BLOCK_pipe_p8
INFO: [VRFC 10-311] analyzing module FP_SUM_BLOCK_pipe_p9
INFO: [VRFC 10-311] analyzing module FP_SUM_BLOCK_pipe_p10
INFO: [VRFC 10-311] analyzing module FP_SUM_BLOCK_pipe_p11
INFO: [VRFC 10-311] analyzing module FP_SUM_BLOCK_pipe_p12
INFO: [VRFC 10-311] analyzing module FP_SUM_BLOCK_pipe_p13
INFO: [VRFC 10-311] analyzing module FP_SUM_BLOCK_pipe_p14
INFO: [VRFC 10-311] analyzing module FP_SUM_BLOCK_pipe_p15
INFO: [VRFC 10-311] analyzing module FP_SUM_BLOCK_pipe_p16
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cdp/int_sum_block.v" into library work
INFO: [VRFC 10-311] analyzing module int_sum_block
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_active.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CMAC_CORE_active
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_cfg.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CMAC_CORE_cfg
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_mac.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CMAC_CORE_mac
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_in.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CMAC_CORE_rt_in
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_rt_out.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CMAC_CORE_rt_out
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cmac/NV_NVDLA_CMAC_CORE_slcg.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CMAC_CORE_slcg
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cmac/NV_NVDLA_CMAC_REG_dual.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CMAC_REG_dual
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cmac/NV_NVDLA_CMAC_REG_single.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CMAC_REG_single
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cmac/NV_NVDLA_CMAC_core.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CMAC_core
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cmac/NV_NVDLA_CMAC_reg.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CMAC_reg
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/cmac/NV_NVDLA_cmac.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_cmac
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/csc/NV_NVDLA_CSC_SG_dat_fifo.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CSC_SG_dat_fifo
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CSC_SG_dat_fifo_flopram_rwsa_4x33
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/csc/NV_NVDLA_CSC_SG_wt_fifo.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CSC_SG_wt_fifo
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CSC_SG_wt_fifo_flopram_rwsa_4x20
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/csc/NV_NVDLA_CSC_WL_dec.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CSC_WL_dec
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/csc/NV_NVDLA_CSC_dl.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CSC_dl
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/csc/NV_NVDLA_CSC_dual_reg.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CSC_dual_reg
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/csc/NV_NVDLA_CSC_pra_cell.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CSC_pra_cell
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CSC_PRA_CELL_pipe_p1
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CSC_PRA_CELL_pipe_p2
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CSC_PRA_CELL_pipe_p3
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CSC_PRA_CELL_pipe_p4
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CSC_PRA_CELL_pipe_p5
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/csc/NV_NVDLA_CSC_regfile.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CSC_regfile
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/csc/NV_NVDLA_CSC_sg.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CSC_sg
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/csc/NV_NVDLA_CSC_single_reg.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CSC_single_reg
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/csc/NV_NVDLA_CSC_slcg.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CSC_slcg
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/csc/NV_NVDLA_CSC_wl.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_CSC_wl
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/csc/NV_NVDLA_csc.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_csc
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/glb/NV_NVDLA_GLB_CSB_reg.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_GLB_CSB_reg
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/glb/NV_NVDLA_GLB_csb.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_GLB_csb
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/glb/NV_NVDLA_GLB_fc.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_GLB_fc
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/glb/NV_NVDLA_GLB_ic.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_GLB_ic
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/glb/NV_NVDLA_glb.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_glb
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_DMAIF_rdreq.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_DMAIF_rdreq
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_DMAIF_rdrsp.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_DMAIF_rdrsp
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_DMAIF_wr.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_DMAIF_wr
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_nocif.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_nocif
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_dram.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_dram
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_read.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_read
INFO: [VRFC 10-2458] undeclared symbol eg2ig_axi_vld, assumed default net type wire [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_read.v:321]
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_cq.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_READ_cq
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_eg.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_READ_eg
INFO: [VRFC 10-2458] undeclared symbol src7_req, assumed default net type wire [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_eg.v:698]
INFO: [VRFC 10-2458] undeclared symbol src8_req, assumed default net type wire [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_eg.v:701]
INFO: [VRFC 10-2458] undeclared symbol src9_req, assumed default net type wire [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_eg.v:704]
INFO: [VRFC 10-2458] undeclared symbol src10_req, assumed default net type wire [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_eg.v:707]
INFO: [VRFC 10-2458] undeclared symbol src11_req, assumed default net type wire [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_eg.v:710]
INFO: [VRFC 10-2458] undeclared symbol src12_req, assumed default net type wire [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_eg.v:713]
INFO: [VRFC 10-2458] undeclared symbol src13_req, assumed default net type wire [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_eg.v:716]
INFO: [VRFC 10-2458] undeclared symbol src14_req, assumed default net type wire [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_eg.v:719]
INFO: [VRFC 10-2458] undeclared symbol src15_req, assumed default net type wire [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_eg.v:722]
INFO: [VRFC 10-2458] undeclared symbol ro0_rd1_pvld, assumed default net type wire [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_eg.v:1018]
INFO: [VRFC 10-2458] undeclared symbol ro1_rd1_pvld, assumed default net type wire [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_eg.v:1070]
INFO: [VRFC 10-2458] undeclared symbol ro2_rd1_pvld, assumed default net type wire [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_eg.v:1122]
INFO: [VRFC 10-2458] undeclared symbol ro3_rd1_pvld, assumed default net type wire [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_eg.v:1174]
INFO: [VRFC 10-2458] undeclared symbol ro4_rd1_pvld, assumed default net type wire [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_eg.v:1226]
INFO: [VRFC 10-2458] undeclared symbol ro5_rd1_pvld, assumed default net type wire [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_eg.v:1278]
INFO: [VRFC 10-2458] undeclared symbol ro6_rd1_pvld, assumed default net type wire [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_eg.v:1330]
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_READ_EG_pipe_p1
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_READ_EG_pipe_p2
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_READ_EG_lat_fifo_flopram_rwsa_4xNVDLA_PRIMARY_MEMIF_WIDTH
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_READ_EG_ro_fifo_flopram_rwsa_4x257
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_ig.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_READ_ig
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_IG_arb.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_READ_IG_arb
INFO: [VRFC 10-2458] undeclared symbol arb_src7_rdy, assumed default net type wire [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_IG_arb.v:349]
INFO: [VRFC 10-2458] undeclared symbol arb_src8_rdy, assumed default net type wire [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_IG_arb.v:352]
INFO: [VRFC 10-2458] undeclared symbol arb_src9_rdy, assumed default net type wire [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_IG_arb.v:355]
INFO: [VRFC 10-2458] undeclared symbol arb_src10_rdy, assumed default net type wire [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_IG_arb.v:358]
INFO: [VRFC 10-2458] undeclared symbol arb_src11_rdy, assumed default net type wire [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_IG_arb.v:361]
INFO: [VRFC 10-2458] undeclared symbol arb_src12_rdy, assumed default net type wire [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_IG_arb.v:364]
INFO: [VRFC 10-2458] undeclared symbol arb_src13_rdy, assumed default net type wire [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_IG_arb.v:367]
INFO: [VRFC 10-2458] undeclared symbol arb_src14_rdy, assumed default net type wire [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_IG_arb.v:370]
INFO: [VRFC 10-2458] undeclared symbol arb_src15_rdy, assumed default net type wire [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_IG_arb.v:373]
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_READ_IG_ARB_pipe_p1
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_IG_bpt.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_READ_IG_bpt
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_READ_IG_BPT_pipe_p1
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_READ_IG_BPT_pipe_p2
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_IG_cvt.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_READ_IG_cvt
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_READ_IG_CVT_pipe_p1
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_READ_IG_spt.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_READ_IG_spt
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_READ_IG_SPT_pipe_p1
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_write.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_write
INFO: [VRFC 10-2458] undeclared symbol eg2ig_axi_vld, assumed default net type wire [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_write.v:187]
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_cq.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_WRITE_cq
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_eg.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_WRITE_eg
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_ig.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_WRITE_ig
INFO: [VRFC 10-2458] undeclared symbol arb2spt_dat_valid, assumed default net type wire [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_ig.v:275]
INFO: [VRFC 10-2458] undeclared symbol arb2spt_dat_ready, assumed default net type wire [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_ig.v:276]
INFO: [VRFC 10-2458] undeclared symbol spt2cvt_dat_valid, assumed default net type wire [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_ig.v:294]
INFO: [VRFC 10-2458] undeclared symbol spt2cvt_dat_ready, assumed default net type wire [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_ig.v:295]
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_IG_arb.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_WRITE_IG_arb
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_WRITE_IG_ARB_dfifo
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_WRITE_IG_ARB_dfifo_flopram_rwsa_4x66
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_WRITE_IG_ARB_pipe_p1
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_IG_bpt.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_WRITE_IG_bpt
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_pipe_p1
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_pipe_p2
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_pipe_p3
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_dfifo
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_WRITE_IG_BPT_dfifo_flopram_rwsa_ram
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_IG_cvt.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_WRITE_IG_cvt
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_WRITE_IG_CVT_pipe_p1
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_WRITE_IG_CVT_pipe_p2
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_WRITE_IG_CVT_pipe_p3
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_WRITE_IG_CVT_pipe_p4
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_NOCIF_DRAM_WRITE_IG_spt.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_WRITE_IG_spt
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_WRITE_IG_SPT_pipe_p1
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_WRITE_IG_SPT_dfifo
INFO: [VRFC 10-311] analyzing module NV_NVDLA_NOCIF_DRAM_WRITE_IG_SPT_dfifo_flopram_rwsa_5x66
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_XXIF_libs.v" into library work
INFO: [VRFC 10-311] analyzing module read_ig_arb
INFO: [VRFC 10-311] analyzing module read_eg_arb
INFO: [VRFC 10-311] analyzing module write_ig_arb
INFO: [VRFC 10-311] analyzing module write_eg_arb
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_CSB_reg.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_MCIF_CSB_reg
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_READ_IG_arb.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_MCIF_READ_IG_arb
INFO: [VRFC 10-311] analyzing module NV_NVDLA_MCIF_READ_IG_ARB_pipe
INFO: [VRFC 10-311] analyzing module NV_NVDLA_MCIF_READ_IG_ARB_pipe_out
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_READ_IG_bpt.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_MCIF_READ_IG_bpt
INFO: [VRFC 10-311] analyzing module NV_NVDLA_MCIF_READ_IG_BPT_pipe_p1
INFO: [VRFC 10-311] analyzing module NV_NVDLA_MCIF_READ_IG_BPT_pipe_p2
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_READ_IG_cvt.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_MCIF_READ_IG_cvt
INFO: [VRFC 10-311] analyzing module NV_NVDLA_MCIF_READ_IG_CVT_pipe_p1
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_READ_eg.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_MCIF_READ_eg
INFO: [VRFC 10-311] analyzing module NV_NVDLA_MCIF_READ_EG_pipe_pr
INFO: [VRFC 10-311] analyzing module NV_NVDLA_MCIF_READ_EG_OUT_pipe
INFO: [VRFC 10-311] analyzing module NV_NVDLA_MCIF_READ_EG_lat_fifo
INFO: [VRFC 10-311] analyzing module NV_NVDLA_MCIF_READ_EG_lat_fifo_flopram_rwsa_4x64
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_READ_ig.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_MCIF_READ_ig
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_WRITE_IG_arb.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_MCIF_WRITE_IG_arb
INFO: [VRFC 10-311] analyzing module NV_NVDLA_MCIF_WRITE_IG_ARB_pipe
INFO: [VRFC 10-311] analyzing module NV_NVDLA_MCIF_WRITE_IG_ARB_dfifo
INFO: [VRFC 10-311] analyzing module NV_NVDLA_MCIF_WRITE_IG_ARB_dfifo_flopram_rwsa_4x65
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_WRITE_IG_bpt.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_MCIF_WRITE_IG_bpt
INFO: [VRFC 10-311] analyzing module NV_NVDLA_MCIF_WRITE_IG_BPT_pipe_p1
INFO: [VRFC 10-311] analyzing module NV_NVDLA_MCIF_WRITE_IG_BPT_pipe_p2
INFO: [VRFC 10-311] analyzing module NV_NVDLA_MCIF_WRITE_IG_BPT_pipe_p3
INFO: [VRFC 10-311] analyzing module NV_NVDLA_MCIF_WRITE_IG_BPT_dfifo
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_WRITE_IG_cvt.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_MCIF_WRITE_IG_cvt
INFO: [VRFC 10-311] analyzing module NV_NVDLA_MCIF_WRITE_IG_CVT_pipe_p1
INFO: [VRFC 10-311] analyzing module NV_NVDLA_MCIF_WRITE_IG_CVT_pipe_p2
INFO: [VRFC 10-311] analyzing module NV_NVDLA_MCIF_WRITE_IG_CVT_pipe_p3
INFO: [VRFC 10-311] analyzing module NV_NVDLA_MCIF_WRITE_IG_CVT_pipe_p4
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_WRITE_cq.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_MCIF_WRITE_cq
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_WRITE_eg.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_MCIF_WRITE_eg
INFO: [VRFC 10-311] analyzing module NV_NVDLA_MCIF_WRITE_EG_pipe
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_WRITE_ig.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_MCIF_WRITE_ig
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_csb.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_MCIF_csb
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_read.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_MCIF_read
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_MCIF_write.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_MCIF_write
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_XXIF_libs.v" into library work
INFO: [VRFC 10-311] analyzing module read_ig_arb
WARNING: [VRFC 10-2845] overwriting previous definition of module read_ig_arb [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_XXIF_libs.v:33]
INFO: [VRFC 10-311] analyzing module read_eg_arb
WARNING: [VRFC 10-2845] overwriting previous definition of module read_eg_arb [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_XXIF_libs.v:1941]
INFO: [VRFC 10-311] analyzing module write_ig_arb
WARNING: [VRFC 10-2845] overwriting previous definition of module write_ig_arb [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_XXIF_libs.v:3800]
INFO: [VRFC 10-311] analyzing module write_eg_arb
WARNING: [VRFC 10-2845] overwriting previous definition of module write_eg_arb [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_XXIF_libs.v:4848]
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/nocif/NV_NVDLA_mcif.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_mcif
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/pdp/NV_NVDLA_PDP_CORE_cal1d.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_PDP_CORE_cal1d
INFO: [VRFC 10-311] analyzing module NV_NVDLA_PDP_cal1d_info_fifo
INFO: [VRFC 10-311] analyzing module NV_NVDLA_PDP_cal1d_info_fifo_flopram_rwsa_8x12
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/pdp/NV_NVDLA_PDP_CORE_cal2d.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_PDP_CORE_cal2d
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/pdp/NV_NVDLA_PDP_CORE_preproc.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_PDP_CORE_preproc
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/pdp/NV_NVDLA_PDP_CORE_unit1d.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_PDP_CORE_unit1d
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_REG_dual.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_PDP_RDMA_REG_dual
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_REG_single.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_PDP_RDMA_REG_single
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_cq.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_PDP_RDMA_cq
INFO: [VRFC 10-311] analyzing module NV_NVDLA_PDP_RDMA_cq_flopram_rwsa_256x18
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_eg.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_PDP_RDMA_eg
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_ig.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_PDP_RDMA_ig
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/pdp/NV_NVDLA_PDP_RDMA_reg.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_PDP_RDMA_reg
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/pdp/NV_NVDLA_PDP_REG_dual.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_PDP_REG_dual
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/pdp/NV_NVDLA_PDP_REG_single.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_PDP_REG_single
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/pdp/NV_NVDLA_PDP_WDMA_cmd.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_PDP_WDMA_cmd
INFO: [VRFC 10-311] analyzing module NV_NVDLA_PDP_WDMA_CMD_fifo
INFO: [VRFC 10-311] analyzing module NV_NVDLA_PDP_WDMA_CMD_fifo_flopram_rwsa_1x80
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/pdp/NV_NVDLA_PDP_WDMA_dat.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_PDP_WDMA_dat
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/pdp/NV_NVDLA_PDP_core.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_PDP_core
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/pdp/NV_NVDLA_PDP_nan.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_PDP_nan
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/pdp/NV_NVDLA_PDP_rdma.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_PDP_rdma
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/pdp/NV_NVDLA_PDP_reg.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_PDP_reg
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/pdp/NV_NVDLA_PDP_slcg.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_PDP_slcg
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/pdp/NV_NVDLA_PDP_wdma.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_PDP_wdma
INFO: [VRFC 10-311] analyzing module NV_NVDLA_PDP_WDMA_intr_fifo
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/pdp/NV_NVDLA_pdp.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_pdp
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/pdp/cal1d_fp16_pool_sum.v" into library work
INFO: [VRFC 10-311] analyzing module cal1d_fp16_pool_sum
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/pdp/fp16_4add.v" into library work
INFO: [VRFC 10-311] analyzing module fp16_4add
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/retiming/NV_NVDLA_RT_cacc2glb.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_RT_cacc2glb
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/retiming/NV_NVDLA_RT_cmac_a2cacc.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_RT_cmac_a2cacc
INFO: [VRFC 10-2458] undeclared symbol mac2accu_data0_d0, assumed default net type wire [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/retiming/NV_NVDLA_RT_cmac_a2cacc.v:118]
INFO: [VRFC 10-2458] undeclared symbol mac2accu_data1_d0, assumed default net type wire [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/retiming/NV_NVDLA_RT_cmac_a2cacc.v:119]
INFO: [VRFC 10-2458] undeclared symbol mac2accu_data2_d0, assumed default net type wire [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/retiming/NV_NVDLA_RT_cmac_a2cacc.v:120]
INFO: [VRFC 10-2458] undeclared symbol mac2accu_data3_d0, assumed default net type wire [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/retiming/NV_NVDLA_RT_cmac_a2cacc.v:121]
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_RT_cmac_b2cacc
INFO: [VRFC 10-2458] undeclared symbol mac2accu_data0_d0, assumed default net type wire [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:118]
INFO: [VRFC 10-2458] undeclared symbol mac2accu_data1_d0, assumed default net type wire [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:119]
INFO: [VRFC 10-2458] undeclared symbol mac2accu_data2_d0, assumed default net type wire [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:120]
INFO: [VRFC 10-2458] undeclared symbol mac2accu_data3_d0, assumed default net type wire [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/retiming/NV_NVDLA_RT_cmac_b2cacc.v:121]
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/retiming/NV_NVDLA_RT_csb2cacc.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_RT_csb2cacc
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/retiming/NV_NVDLA_RT_csb2cmac.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_RT_csb2cmac
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/retiming/NV_NVDLA_RT_csc2cmac_a.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_RT_csc2cmac_a
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/retiming/NV_NVDLA_RT_csc2cmac_b.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_RT_csc2cmac_b
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/rubik/NV_NVDLA_RUBIK_dma.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_RUBIK_dma
INFO: [VRFC 10-311] analyzing module NV_NVDLA_RUBIK_DMA_pipe_p1
INFO: [VRFC 10-311] analyzing module NV_NVDLA_RUBIK_DMA_pipe_p3
INFO: [VRFC 10-311] analyzing module NV_NVDLA_RUBIK_DMA_pipe_p5
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/rubik/NV_NVDLA_RUBIK_dr2drc.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_RUBIK_dr2drc
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/rubik/NV_NVDLA_RUBIK_dual_reg.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_RUBIK_dual_reg
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/rubik/NV_NVDLA_RUBIK_fifo.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_RUBIK_fifo
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/rubik/NV_NVDLA_RUBIK_intr.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_RUBIK_intr
INFO: [VRFC 10-311] analyzing module NV_NVDLA_RUBIK_opdone_fifo
INFO: [VRFC 10-311] analyzing module NV_NVDLA_RUBIK_opdone_fifo_flopram_rwsa_4x1
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/rubik/NV_NVDLA_RUBIK_regfile.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_RUBIK_regfile
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/rubik/NV_NVDLA_RUBIK_rf_core.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_RUBIK_rf_core
INFO: [VRFC 10-311] analyzing module NV_NVDLA_RUBIK_RF_CORE_pipe_p1
INFO: [VRFC 10-311] analyzing module NV_NVDLA_RUBIK_RF_CORE_pipe_p2
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/rubik/NV_NVDLA_RUBIK_rf_ctrl.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_RUBIK_rf_ctrl
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/rubik/NV_NVDLA_RUBIK_rf_rcmd.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_RUBIK_rf_rcmd
INFO: [VRFC 10-311] analyzing module NV_NVDLA_RUBIK_rf_rcmd_flopram_rwsa_4x12
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/rubik/NV_NVDLA_RUBIK_rf_wcmd.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_RUBIK_rf_wcmd
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/rubik/NV_NVDLA_RUBIK_seq_gen.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_RUBIK_seq_gen
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/rubik/NV_NVDLA_RUBIK_single_reg.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_RUBIK_single_reg
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/rubik/NV_NVDLA_RUBIK_slcg.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_RUBIK_slcg
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/rubik/NV_NVDLA_RUBIK_wr_req.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_RUBIK_wr_req
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_cmd.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_RUBIK_wrdma_cmd
INFO: [VRFC 10-311] analyzing module NV_NVDLA_RUBIK_wrdma_cmd_flopram_rwsa_4x73
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/rubik/NV_NVDLA_RUBIK_wrdma_data.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_RUBIK_wrdma_data
INFO: [VRFC 10-311] analyzing module NV_NVDLA_RUBIK_wrdma_data_flopram_rwsa_4x256
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/rubik/NV_NVDLA_rubik.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_rubik
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_BRDMA_cq_lib.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_SDP_BRDMA_cq_256x16
INFO: [VRFC 10-311] analyzing module NV_NVDLA_SDP_BRDMA_cq_64x16
INFO: [VRFC 10-311] analyzing module NV_NVDLA_SDP_BRDMA_cq_16x16
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_BRDMA_gate.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_SDP_BRDMA_gate
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_BRDMA_lat_fifo_lib.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_SDP_BRDMA_lat_fifo_256x257
INFO: [VRFC 10-311] analyzing module NV_NVDLA_SDP_BRDMA_lat_fifo_64x129
INFO: [VRFC 10-311] analyzing module NV_NVDLA_SDP_BRDMA_lat_fifo_16x65
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_y.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_SDP_CORE_y
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_Y_lut.v" into library work
INFO: [VRFC 10-311] analyzing module NV_NVDLA_SDP_CORE_Y_lut
ERROR: [VRFC 10-91] lut_in_oflow0 is not declared [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_Y_lut.v:22012]
ERROR: [VRFC 10-91] lut_in_uflow0 is not declared [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_Y_lut.v:22062]
ERROR: [VRFC 10-91] lut_in_hybrid0 is not declared [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_Y_lut.v:22117]
ERROR: [VRFC 10-91] lut_in_le_hit0 is not declared [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_Y_lut.v:22169]
ERROR: [VRFC 10-91] lut_in_lo_hit0 is not declared [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_Y_lut.v:22221]
ERROR: [VRFC 10-2787] module NV_NVDLA_SDP_CORE_Y_lut ignored due to previous errors [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_Y_lut.v:18]
INFO: [VRFC 10-311] analyzing module NV_NVDLA_SDP_CORE_Y_lut_pipe_p1
WARNING: [VRFC 10-143] lut_in_pd was previously declared with a range [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_Y_lut.v:22687]
ERROR: [VRFC 10-2787] module NV_NVDLA_SDP_CORE_Y_lut_pipe_p1 ignored due to previous errors [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_Y_lut.v:22653]
INFO: [VRFC 10-311] analyzing module NV_NVDLA_SDP_CORE_Y_lut_pipe_p2
WARNING: [VRFC 10-143] lut2inp_pd was previously declared with a range [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_Y_lut.v:22784]
ERROR: [VRFC 10-2787] module NV_NVDLA_SDP_CORE_Y_lut_pipe_p2 ignored due to previous errors [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_Y_lut.v:22750]
INFO: [VRFC 10-311] analyzing module NV_NVDLA_SDP_CORE_Y_LUT_dat
ERROR: [VRFC 10-2787] module NV_NVDLA_SDP_CORE_Y_LUT_dat ignored due to previous errors [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_Y_lut.v:22849]
INFO: [VRFC 10-311] analyzing module NV_NVDLA_SDP_CORE_Y_LUT_dat_flopram_rwsa_2x128
ERROR: [VRFC 10-2787] module NV_NVDLA_SDP_CORE_Y_LUT_dat_flopram_rwsa_2x128 ignored due to previous errors [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_Y_lut.v:23114]
INFO: [VRFC 10-311] analyzing module NV_NVDLA_SDP_CORE_Y_LUT_cmd
ERROR: [VRFC 10-2787] module NV_NVDLA_SDP_CORE_Y_LUT_cmd ignored due to previous errors [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_Y_lut.v:23271]
INFO: [VRFC 10-311] analyzing module NV_NVDLA_SDP_CORE_Y_LUT_cmd_flopram_rwsa_2x280
ERROR: [VRFC 10-2787] module NV_NVDLA_SDP_CORE_Y_LUT_cmd_flopram_rwsa_2x280 ignored due to previous errors [/home/esa/jyj/nvdla_2/hw/outdir/nv_small/vmod/nvdla/sdp/NV_NVDLA_SDP_CORE_Y_lut.v:23597]
Vivado Simulator 2018.2
Copyright 1986-1999, 2001-2018 Xilinx, Inc. All Rights Reserved.
Running: /opt/Xilinx/Vivado/2018.2/bin/unwrapped/lnx64.o/xelab top --debug all
Multi-threading is on. Using 6 slave threads.
ERROR: [XSIM 43-3225] Cannot find design unit work.top in library work located at xsim.dir/work.
Makefile:471: recipe for target 'build' failed
make: *** [build] Error 1

In file 'NV_NVDLA_SDP_CORE_Y_lut.v', I found a line

include "simulate_x_tick.vh"

but I can't find this file in any folder. any help or guide to vivado support for master(v2) branch? thanks in advance.