Implementation of NVIDIA accelerator in an FPGA

nvdla / hw

RTL, Cmodel, and testbench for NVDLA

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Implementation of NVIDIA accelerator in an FPGA #292

Open gitosu67 opened 5 years ago

gitosu67 commented 5 years ago

Hi,

I am working on implementing the NVDLA in a Xilinx FPGA. I am using the Vivado tool for the same. So far I know that I have to generate the custom IP's for the NVDLA and the AXI interconnect and create a wrapper of them. But, I am stuck on how to create the IP for the NVDLA block. I am really new in this field and If someone can elaborate on the steps it will be of great help.

Thank you

Ahmed1Zaky commented 5 years ago

Hey, have you managed to do it ? I am trying to do the same.

gitosu67 commented 5 years ago

Nope, not yet. I am following this thread for reference: https://github.com/nvdla/hw/issues/110

shazib-summar commented 4 years ago

Any update guys?

nagendra7890 commented 3 years ago

Hi, @Okaymaddy Did you solve the issue?

I am also trying to do the same but getting errors at the synthesis stage. can you please help me to sort it out?

Please see the below-attached file.

Thank You.