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NV_BLKBOX_SINK error in vivado / FPGA implementation #303

Open gitosu67 opened 4 years ago

gitosu67 commented 4 years ago

Hi all,

I am getting the following error while trying to synthesize my design for implementing NVDLA on an FPGA. I am using the Zynq ultrascale+ family.

_[Project 1-486] Could not resolve non-primitive black box cell 'design_1_design_1_wrapper_0_0_NV_BLKBOX_SINK_HD1725' instantiated as 'design_1_i/design_1_wrapper_0/inst/design_1_i/NV_nvdla_0/inst/u_partition_p/u_NV_NVDLA_sdp/u_rdma/u_nrdma/u_lat_fifo/ram/r_nv_ram_rwsp_16x65/UJ_BBOX2UNIT_UNUSED_pwrbus_31' ["/home/user/project_create16/project_create16.srcs/sources_1/bd/design_1/ip/design_1_design_1_wrapper_0_0/ipshared/ab69/src/nv_ram_rwsp_16x65logic.v":132]

One solution I found was to define FPGA macro and set it to 1. I added that in the Defines found in the project settings in Vivado. Also, I added this macro in every possible source files I am using, as: `define FPGA 1. I also made a separate .vh file and have added that as a Global include. But none of this seems to work and I still get the error. Also, I get the BLKBOX error only when I create the wrapper. If I don't create the wrapper and try to connect the combination of (NVDLA IP and NVDLA_apb2csb IP) with the Zynq ultra-scale+ block, the synthesis, and implementation passes.

So my question is, is it not required to create the wrapper? And if it is required, should I be doing anything else to get rid of this error? Any help and suggestions will be highly appreciated. Thank you!

ghost commented 4 years ago

Hi @Okaymaddy

Wrong RAMs imported into the project, and that's all... See vmod/rams/fpga directory. And dla_ramgen just in case some RAMs were missing. These RAMs are much simpler in implementation, because XST synthesis tool will attempt to infer optimal solution (DRAM, BRAM, or URAM).

shazib-summar commented 4 years ago

@mmaciag what is dla_ramgen? Thanks.

gitosu67 commented 4 years ago

@mmaciag Do you think this error is maybe because of some wrong fifo modules (because of different clock names) residing as duplicates in particular engines? If that's the case, should I manually change all the duplicate file's clock names?

ghost commented 4 years ago

@killerzula script available in vmod/rams/fpga (in master branch)

tomenendal commented 3 years ago

Hey there, i am facing a similar issue... I defined all macros and generated the missing rams via dla_ramgen. In my case for vc709 and nv_small it was at least the nv_ram_rwsthp_80x17. Nevertheless there are a view modules calling NV_BLKBOX_SINK, in nvdla it is the case for NV_NVDLA_CDP_RDMA_cq NV_NVDLA_MCIF_READ_EG_lat_fifo NV_NVDLA_MCIF_WRITE_IG_ARB_dfifo NV_NVDLA_PDP_RDMA_cq, from the fifos it is NV_NVDLA_CDP_RDMA_ro_fifo NV_NVDLA_CDP_WDMA_dat_fifo NV_NVDLA_PDP_RDMA_ro_fifo NV_NVDLA_PDP_SDPIN_ro_fifo NV_NVDLA_PDP_WDMA_DAT_fifo. All calling modules in there are named like "flopram_rwsa_ABCxDEF". Did someone face such issue or knows how to proceed from here?

nagendra7890 commented 3 years ago

Hi, @Okaymaddy I am stuck at the synthesis stage. If I consider the top module as NVDLA, showing modules files are not found. I tried to change the Verilog files as Global include. But still facing the same problem. If anyone solved this problem please help me to sort it out.

Please see the below-attached error file. Thank You.

image

tirumalnaidu commented 3 years ago

@Okaymaddy @tomenendal Are you able to solve this NV_BLKBOX_SINK error?

tirumalnaidu commented 3 years ago

For me, using nv_small branch instead of master branch for generating the verilog codes (vmod) solved this error.

nagendra7890 commented 3 years ago

Hi, @tirumalnaidu did you implemented on Vivado?

tirumalnaidu commented 3 years ago

Hi, @tirumalnaidu did you implemented on Vivado?

yes, Vivado 2020.1

Ammadali90 commented 3 years ago

[DRC INBB-3] Black Box Instances: Cell 'u_partition_o/u_NV_NVDLA_cdp/u_rdma/u_cq/ram/UJ_BBOX2UNIT_UNUSED_pwrbus_0' of type u_partition_o/u_NV_NVDLA_pdp/u_wdma/u_dat/u_dat0_fifo7/ram/UJ_BBOX2UNIT_UNUSED_pwrbus_9/NV_BLKBOX_SINK' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.

Did someone solve this issue? I tried to use outdir/nv_small/vmod/rams/fpga/model but it did not solve the problem.

xldeng-chn commented 3 years ago

@Ammadali90 Oh, I got stuck in this error too when implementing, but I found module "NV_BLKBOX_SINK" defines only an input port. image I also have no idea.

yss-pku commented 2 years ago

@xldeng-chn I also got stuck in this error when implementing.Have you solved this problem

xldeng-chn commented 2 years ago

@xldeng-chn I also got stuck in this error when implementing.Have you solved this problem

Which branch are you using? I remember I encountered this problem when I was using the "nv_small" branch. I find that there exist code differences between nv_small and master where the NV_BLKBOX_SINK is instantiated. If you are using nv_small, you can try the master branch, it works well.

ChangAnGuLi commented 2 years ago

[DRC INBB-3] Black Box Instances: Cell 'u_partition_o/u_NV_NVDLA_cdp/u_rdma/u_cq/ram/UJ_BBOX2UNIT_UNUSED_pwrbus_0' of type u_partition_o/u_NV_NVDLA_pdp/u_wdma/u_dat/u_dat0_fifo7/ram/UJ_BBOX2UNIT_UNUSED_pwrbus_9/NV_BLKBOX_SINK' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully.

Did someone solve this issue? I tried to use outdir/nv_small/vmod/rams/fpga/model but it did not solve the problem.

can you reslove this error， please teach me

yss-pku commented 2 years ago

[DRC INBB-3] Black Box Instances: Cell 'u_partition_o/u_NV_NVDLA_cdp/u_rdma/u_cq/ram/UJ_BBOX2UNIT_UNUSED_pwrbus_0' of type u_partition_o/u_NV_NVDLA_pdp/u_wdma/u_dat/u_dat0_fifo7/ram/UJ_BBOX2UNIT_UNUSED_pwrbus_9/NV_BLKBOX_SINK' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully. Did someone solve this issue? I tried to use outdir/nv_small/vmod/rams/fpga/model but it did not solve the problem.

can you reslove this error， please teach me

ADD AN OUTPUT SINGLE,just like module NV_BLKBOX_SINK ( A, B ); input A ; output B; assign B = A; endmodule

ChangAnGuLi commented 2 years ago

[DRC INBB-3] Black Box Instances: Cell 'u_partition_o/u_NV_NVDLA_cdp/u_rdma/u_cq/ram/UJ_BBOX2UNIT_UNUSED_pwrbus_0' of type u_partition_o/u_NV_NVDLA_pdp/u_wdma/u_dat/u_dat0_fifo7/ram/UJ_BBOX2UNIT_UNUSED_pwrbus_9/NV_BLKBOX_SINK' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully. Did someone solve this issue? I tried to use outdir/nv_small/vmod/rams/fpga/model but it did not solve the problem.

can you reslove this error， please teach me

ADD AN OUTPUT SINGLE,just like module NV_BLKBOX_SINK ( A, B ); input A ; output B; assign B = A; endmodule

thanks