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RTL, Cmodel, and testbench for NVDLA
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Cannot build cmod_top for nv_full at nvdlav1 #311

Open shazib-summar opened 4 years ago

shazib-summar commented 4 years ago

Hi. I am trying to build nv_full from the nvdlav1 branch. However, when I run the command ./tools/bin/tmake -build cmod_top I get the following output

`make: Entering directory '/home/user01/Documents/NVDLA/nvdla1/spec/defs' /usr/bin/cpp-4.8 -undef -nostdinc -P -C nv_full.spec -o /home/user01/Documents/NVDLA/nvdla1/outdir/nv_full/spec/defs/project.def ../../tools/bin/defgen -i /home/user01/Documents/NVDLA/nvdla1/outdir/nv_full/spec/defs/project.def -o /home/user01/Documents/NVDLA/nvdla1/outdir/nv_full/spec/defs/project.h -b c ../../tools/bin/defgen -i /home/user01/Documents/NVDLA/nvdla1/outdir/nv_full/spec/defs/project.def -o /home/user01/Documents/NVDLA/nvdla1/outdir/nv_full/spec/defs/project.vh -b v

files are generated under /home/user01/Documents/NVDLA/nvdla1/outdir/nv_full/spec/defs

make: Leaving directory '/home/user01/Documents/NVDLA/nvdla1/spec/defs' make: Entering directory '/home/user01/Documents/NVDLA/nvdla1/spec/manual' /usr/bin/java -jar Ordt.jar -parms test.parms -systemverilog /home/user01/Documents/NVDLA/nvdla1/outdir/nv_full/spec/manual/sv/ -verilog /home/user01/Documents/NVDLA/nvdla1/outdir/nv_full/spec/manual/regs_v.v -uvmregs /home/user01/Documents/NVDLA/nvdla1/outdir/nv_full/spec/manual/regs_ral.sv -cppmod /home/user01/Documents/NVDLA/nvdla1/outdir/nv_full/spec/manual/cmod -cppdrvmod /home/user01/Documents/NVDLA/nvdla1/outdir/nv_full/spec/manual/dmod test.rdl Open Register Design Tool, version=170915.01, input=test.rdl Ordt: reading parameters from test.parms... Ordt: building verilog... Ordt: writing verilog file /home/user01/Documents/NVDLA/nvdla1/outdir/nv_full/spec/manual/regs_v.v... Ordt: building systemverilog... Ordt: writing systemverilog file /home/user01/Documents/NVDLA/nvdla1/outdir/nv_full/spec/manual/sv/simple1_pio.sv... Ordt: writing systemverilog file /home/user01/Documents/NVDLA/nvdla1/outdir/nv_full/spec/manual/sv/simple1_jrdl_logic.sv... Ordt: writing systemverilog file /home/user01/Documents/NVDLA/nvdla1/outdir/nv_full/spec/manual/sv/simple1_jrdl_decode.sv... Ordt: building UVM regs... Ordt: writing UVM regs file /home/user01/Documents/NVDLA/nvdla1/outdir/nv_full/spec/manual/regs_ral.sv... Ordt: building C++ model... WARNING : C++ model does not support non-zero init values for wide fields, field=value Ordt: writing C++ model file /home/user01/Documents/NVDLA/nvdla1/outdir/nv_full/spec/manual/cmod/ordt_pio_common.hpp... Ordt: writing C++ model file /home/user01/Documents/NVDLA/nvdla1/outdir/nv_full/spec/manual/cmod/ordt_pio_common.cpp... Ordt: writing C++ model file /home/user01/Documents/NVDLA/nvdla1/outdir/nv_full/spec/manual/cmod/ordt_pio.hpp... Ordt: writing C++ model file /home/user01/Documents/NVDLA/nvdla1/outdir/nv_full/spec/manual/cmod/ordt_pio.cpp... Ordt: building C++ driver model... INFO : Overlay 0 total processed instances=16, unique instances=16, duplicate instances=0 Ordt: writing C++ driver model file /home/user01/Documents/NVDLA/nvdla1/outdir/nv_full/spec/manual/dmod/ordt_pio_common.hpp... Ordt: writing C++ driver model file /home/user01/Documents/NVDLA/nvdla1/outdir/nv_full/spec/manual/dmod/ordt_pio_common.cpp... Ordt: writing C++ driver model file /home/user01/Documents/NVDLA/nvdla1/outdir/nv_full/spec/manual/dmod/ordt_pio_drv.hpp... Ordt: writing C++ driver model file /home/user01/Documents/NVDLA/nvdla1/outdir/nv_full/spec/manual/dmod/ordt_pio_drv.cpp... Ordt complete Wed Oct 16 21:42:26 PKT 2019

@cp -f /home/user01/Documents/NVDLA/nvdla1/outdir/nv_full/spec/manual/regs_v.v /home/user01/Documents/NVDLA/nvdla1/outdir/nv_full/spec/manual/; rm /home/user01/Documents/NVDLA/nvdla1/outdir/nv_full/spec/manual/regs_v.v -rf

@cp -f /home/user01/Documents/NVDLA/nvdla1/outdir/nv_full/spec/manual/regs_ral.sv /home/user01/Documents/NVDLA/nvdla1/outdir/nv_full/spec/manual/; rm /home/user01/Documents/NVDLA/nvdla1/outdir/nv_full/spec/manual/regs_ral.sv -rf

@cp -rf /home/user01/Documents/NVDLA/nvdla1/outdir/nv_full/spec/manual/sv/ /home/user01/Documents/NVDLA/nvdla1/outdir/nv_full/spec/manual/; rm /home/user01/Documents/NVDLA/nvdla1/outdir/nv_full/spec/manual/sv/ -rf

@cp -rf /home/user01/Documents/NVDLA/nvdla1/outdir/nv_full/spec/manual/cmod /home/user01/Documents/NVDLA/nvdla1/outdir/nv_full/spec/manual/; rm /home/user01/Documents/NVDLA/nvdla1/outdir/nv_full/spec/manual/cmod -rf

@cp -rf /home/user01/Documents/NVDLA/nvdla1/outdir/nv_full/spec/manual/dmod /home/user01/Documents/NVDLA/nvdla1/outdir/nv_full/spec/manual/; rm /home/user01/Documents/NVDLA/nvdla1/outdir/nv_full/spec/manual/dmod -rf

============================================== files are generated under /home/user01/Documents/NVDLA/nvdla1/outdir/nv_full/spec/manual

make: Leaving directory '/home/user01/Documents/NVDLA/nvdla1/spec/manual' make: Entering directory '/home/user01/Documents/NVDLA/nvdla1/cmod' mkdir -p ../outdir/nv_full/cmod/release/lib mkdir -p ../outdir/nv_full/cmod/release/include cp -f ../outdir/nv_full/cmod/libnvdla_cmod.so ../outdir/nv_full/cmod/release/lib cp -f ../cmod/include/scsim_common.h ../outdir/nv_full/cmod/release/include cp -f ../cmod/include/NV_nvdla_top_base.h ../outdir/nv_full/cmod/release/include cp -f ../cmod/nvdla_top/NV_nvdla.h ../outdir/nv_full/cmod/release/include

release files are installed to ../outdir/nv_full/cmod/release

============================================== files are generated under /home/user01/Documents/NVDLA/nvdla1/outdir/nv_full/cmod

make: Leaving directory '/home/user01/Documents/NVDLA/nvdla1/cmod' logfile: outdir/build.log

Filehandle GEN1 opened only for input at /home/user01/perl5/perlbrew/perls/perl-5.10.1/lib/site_perl/5.10.1/IO/Tee.pm line 132. ==================BUILD PASS================== Filehandle GEN1 opened only for input at /home/user01/perl5/perlbrew/perls/perl-5.10.1/lib/site_perl/5.10.1/IO/Tee.pm line 132.

Filehandle GEN1 opened only for input at /home/user01/perl5/perlbrew/perls/perl-5.10.1/lib/site_perl/5.10.1/IO/Tee.pm line 132. ` Which as you can tell is not the desired output. My tree.make file is

##=======================
## Project Name Setup, multiple projects supported
##=======================
PROJECTS := nv_full

##=======================
##Linux Environment Setup
##=======================

## c pre-processor
# CPP := /home/utils/gcc-4.9.3/bin/cpp CPP := /usr/bin/cpp-4.8

## c++ compiler
# GCC := /home/utils/gcc-4.9.3/bin/g++ GCC := /usr/bin/g++-4.8

## perl: many scripts is written in perl # PERL := /home/utils/perl-5.8.8/bin/perl #PERL := /usr/bin/perl PERL := /home/user01/perl5/perlbrew/perls/perl-5.10.1/bin/perl

Any help would be extremely appreciated...

## java: used in hardware regester spec compilation (not in current release) # JAVA := /home/utils/java/jdk1.8.0_131/bin/java JAVA := /usr/bin/java

## systemc: needed for Cmodel build (optional) SYSTEMC := /usr/local/systemc-2.3.0/

## verilator: used to build testbench without VCS (optional) VERILATOR := /usr/local/bin/verilator

## clang: used to build Verilated binaries (optional) CLANG := /usr/local/clang