nvdla / hw

RTL, Cmodel, and testbench for NVDLA
Other
1.72k stars 567 forks source link

A Question For RTL Code : tieoff_fifo_depth in different module has different values. How to understand the values? #337

Open Scriabing opened 3 years ago

Scriabing commented 3 years ago

For exmaple , CDP has a 61x66 fifo in CDP_rdma.eg . I know that Tieoff_fifo_pop from eg can control axi READ . why is 61? what decides 61? PDP is same as CDP. why is SDP different ?