Regarding IP creation for NVDLA using VIvado

[nagendra7890]

I am stuck at the synthesis stage. If I consider the top module as NVDLA, showing modules files are not found. I tried to change the Verilog files as Global include. But still facing the same problem. If anyone solved this problem please help me to sort it out. Please see the below-attached error file.

Thank You.

[qaziullah]

@nagendra7890 did you get to generate vmod(verilog model) correctly . I am getting error while executing ./tools/bin/tmake -build vmod

*** No rule to make target 'NV_full.spec'

thanks for the help in advance

[nagendra7890]

hello, @qaziullah I am also getting the same error. if someone solve please help me to sort it out

Thank You.

[qaziullah]

@nagendra7890 which branch are you using? The way it worked for me was that I used the name of project same as the branch name. if you are using nv_small branch then try naming the project nv_small and then go on with ./tools/bin/make -build vmod.

Just name the project the same as the branch (nv_small or nv_full) and make sure that there is no spell or case difference.

[nagendra7890]

@qaziullah I changed to nv_small. I am able to generate cmod code but not vmod.do we need to add a project.h file in nv_small?

[qaziullah]

Have you installed all the tool required as shown in the figure.