rams model clarification

[HaogeL]

Hi, maybe a dumb question: After nv_small is built. vmod/rams directory contains 3 folders: fpga/, model/, and synth/. There is little description about how SRAM is used by NVDLA:

The memories instantiated in the NVDLA design have a logical interface which is fairly common across RAM compilers. The release contains a behavioral model for these RAMS which can be used for simulation. For synthesis, these behavioral models will need to be replaced with a Verilog wrapper which maps to RAM cells from a local library.

How are the rams in the 3 folders are used? which one to use if I want to use different simulator and synthesis tool other than VCS and DC? Here is my guess, are they correct?

• rams in synth/ folder are used when the included sythesis flow starts
• rams in model/ folder are used when simulation flow starts
• rams in fpga/ folder are used by fpga design to infer special ram

[tirumalnaidu]

Yes, you are right synth/ folder can be used for ASIC synthesis tools such as Synopsys DC model/ folder is used for simulations in Synopsys DC and Verilator fpga/ folder is used for instantiations of RAM in Vivado and other FPGA synthesis tools.