How to analysis .dimg format file and use NN_L01_small_fbuf

[robbietoo]

Hi ALL, nv_small on FPGA all Sanity test and NN_L01_small_fbuf TEST PASS, md5sum output.dimg equal golden/.dimg. BUT, golden/.dimg format file output garbled, ./nvdla_runtime --loadable NN_L01_small_fbuf --rawdump --normalize 1 --image fish.jpg get an length of output array: 142560 and output.dimg no change

How to analysis .dimg format file and use NN_L01_small_fbuf ?

[robotcn]

@robbietoo I'm also running NN_L0_1_small_fbuf on FPGA with 100MHz, but it's always stall at "submitting task" even wait for hours time. What's your FPGA frequency, and how about the running time of NN case? Thanks.

[robbietoo]

@robotcn You need to print kernel information to the console. Which FPGA platform do you use? I guess maybe cpu is waiting for interrupt of dla.

[ddkkevin]

@robotcn have you disable clock gate in FPGA？

[robotcn]

@robbietoo @ddkkevin Thanks for your reply. I'm using xilinx FPGA, zynqmp soc, the board is zcu102. The nvdla IP is running at 100MHz. @ddkkevin Do you mean I have to disable clock gate in FPGA for running this NN small test case? Could you kindly tell me how to disable it if it's just some macro enable/disable? I just asked our hw engineer, he told me each submoudle of nvdla has its own clock gate logic, and he said if disable all clock gates, there will be error in functinality. Thanks first.

[ddkkevin]

@robotcn For nv_small design, you should define NV_FPGA_FIFOGEN and VLIB_BYPASS_POWER_CG to disable clock gate logic.

[robbietoo]

@robotcn You need to print kernel information to the console. Our platform and frequency are same. My method is to use vivado synth gate conversion without defining VLIB_BYPASS_POWER_CG and NV_FPGA_FIFOGEN.

[robotcn]

@robbietoo @ddkkevin Thanks for your reply, after define some clcok gate related macros, the NN small test case passed on our FPGA platform now. But another problem is the output.dimg doesn't change if I use --image to specify an input for this network. I checked the umd codes, seems it will parse the input number from flatbuf, but the NN_small flatbuf doesn't contain any input. Do you have any suggestions about this? Thanks.

[robbietoo]

The NN_L0_1 of nv_full is also unaffected by the input options of nvdla_runtime.

[robotcn]

Seems following thread could get confidence result by input image. https://github.com/nvdla/sw/issues/80

[giusecesa4]

@robotcn the flatbufs test have their own input image, so even if you try to put an image to be analyzed, the result will be Always the same

[LeXiaoCCNU]

@robbietoo @robotcn @ddkkevin Hello all, I think you all had test your NV_SMALL on FPGA platform. I want to test NV_SMALL on zcu102 FPGA. I have several questions right now:

1. The current nvdla_compiler does not support NV_SMALL. Is the loadable source you are using only coming from the in the folder under sw/regression/flatbufs/ ? What is the role of the files under the sw/regression/golden/ ?
2. What is the linux version you are using? Do nvdla_runtime, drm.ko and opendla_small.ko need to be recompiled?

[giusecesa4]

1. The files under the sw/regression/golden/ represent the golden results of the NVDLA for the different tests. If you run the test with the option --rawdump the output file becomes readable.
2. Unless you are using the Linux version 4.13.3, the opendla_small.ko must be recompiled for the version you are using. Concerning the drm.ko file, if you are using a linux version for Xilinx you don't need to insert it, it is already in the kernel

[robbietoo]

@LeXiaoCCNU First question, @giusecesa4 already answered. Second, I use Linux version 4.9, rebuild opendla.ko, but do not recompile nvdla_runtime and do not use drm.ko.

[nookfoo]

Have you found out what to do with results or interpret rawdump of output.dimg? I have NN_L01_small_fbuf test passed on zcu102 FPGA and am trying to verify inference results. My output.dimg consists of one long line with numbers which I'm not sure how ro read:

output.dimg.txt

[honorpeter]

Due to the current official release of compiter does not support nv_smal nvdla core. But how do you run NN like Alexnet in Cafe and ResNet 50 with nv_small? How to use NN_L0_1_small_fbuf on FPGA with nv_small? Could you help me?