Open Ristovski opened 2 years ago
Some STM32 SVDs (like STM32L051x.svd) do not provide an explicit SysTick (STK) peripheral.
STM32L051x.svd
STK
In Renode, these are handled implicitly inside their NVIC peripheral: https://github.com/renode/renode-infrastructure/blob/8da5a9d744a4b1048b3affb02a755161fdd477cc/src/Emulator/Cores/Arm-M/NVIC.cs#L723
This is why with Renode, one needs to set the address of NVIC to 0xE000E000 instead of 0xE000E100.
0xE000E000
0xE000E100
Currently, this causes the execution to stall:
[clk=01572483 pc=0x080049e6] TRACE read: addr=0xe000e018 peri=???? read=0x00000000 [clk=01572560 pc=0x080049e6] TRACE read: addr=0xe000e018 peri=???? read=0x00000000 [clk=01572637 pc=0x080049e6] TRACE read: addr=0xe000e018 peri=???? read=0x00000000 [clk=01572714 pc=0x080049e6] TRACE read: addr=0xe000e018 peri=???? read=0x00000000 [clk=01572791 pc=0x080049e6] TRACE read: addr=0xe000e018 peri=???? read=0x00000000
Judging by the Renode NVIC implementation (SysTickValue = 0x18) it seems to be trying to read the SysTick value.
SysTickValue = 0x18
It would be a good idea to add an arm.svd containing the arm cortex core register definitions
arm.svd
Can you prepare such SVD?
Some STM32 SVDs (like
STM32L051x.svd
) do not provide an explicit SysTick (STK
) peripheral.In Renode, these are handled implicitly inside their NVIC peripheral: https://github.com/renode/renode-infrastructure/blob/8da5a9d744a4b1048b3affb02a755161fdd477cc/src/Emulator/Cores/Arm-M/NVIC.cs#L723
This is why with Renode, one needs to set the address of NVIC to
0xE000E000
instead of0xE000E100
.Currently, this causes the execution to stall:
Judging by the Renode NVIC implementation (
SysTickValue = 0x18
) it seems to be trying to read the SysTick value.