When implementing multiple FLEXIO SPIs, the parent interrupt handler calls all child interrupt handlers in turn, for example FLEXIO_SPI_MasterTransferHandleIRQ().
The problem appears when the interrupt is generated by one interface, and in another interface the send buffer is empty
(kFLEXIO_SPI_TxBufferEmptyFlag is set), and there is no data in the receive buffer yet (kFLEXIO_SPI_RxBufferFullFlag is not set), then without waiting for data in the receive buffer, the handler will send new data, which will result in to data loss (SHIFTBUF Overrun). Since in SPI MASTER mode an interrupt is generated only when the receive buffer is full, the child interrupt handler should only be executed when the receive buffer is full.
When implementing multiple FLEXIO SPIs, the parent interrupt handler calls all child interrupt handlers in turn, for example FLEXIO_SPI_MasterTransferHandleIRQ(). The problem appears when the interrupt is generated by one interface, and in another interface the send buffer is empty (kFLEXIO_SPI_TxBufferEmptyFlag is set), and there is no data in the receive buffer yet (kFLEXIO_SPI_RxBufferFullFlag is not set), then without waiting for data in the receive buffer, the handler will send new data, which will result in to data loss (SHIFTBUF Overrun). Since in SPI MASTER mode an interrupt is generated only when the receive buffer is full, the child interrupt handler should only be executed when the receive buffer is full.
Signed-off-by: Mikhail Siomin mikhail.siomin@nxp.com
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