Closed manuargue closed 1 year ago
cc @mmahadevan108 @dleach02
@mcuxsusan . The S32 team is reusing the SDK driver for the work they do in Zephyr. They have a hardware issue for which this workaround is needed. Can you please help review and integrate.
LPSPI in S32K3X4 is affected by errata ERR050456 as described in S32K3X4-0P55A-1P55A-ERRATA document.
The user can reset the transmit FIFO using LPSPIn_CR[RTF] bit and can reset the receive FIFO using LPSPIn_CR[RRF]. However, resetting the FIFO using CR[RTF] and CR[RRF] does not clear the FIFO pointers completely. Workaround this by resetting resetting the entire module using LPSPIn_CR[RST] bit.
Prerequisites
Describe the pull request NXP have introduced support for S32K3 SoCs to Zephyr RTOS (see https://github.com/zephyrproject-rtos/zephyr/pull/58332) and that port reuse existing Zephyr shim drivers -which are backed by MCUX SDK baremetal drivers- for the hardware blocks that are common between the S32K3 devices and other NXP devices.
LPSPI is one these reused drivers. S32K344 version currently supported in Zephyr boards, is affected by errata ERR050456 (
LPSPI: Reset to fifo does not work as expected
) as described in https://www.nxp.com/webapp/Download?colCode=S32K3X4-0P55A-1P55A-ERRATA. This patch implements the first workaround described in this document.This feature is being used in https://github.com/zephyrproject-rtos/hal_nxp/pull/250/files#diff-6b55f3d19303119b783fb5e686289dab902cc3dc0a00759018cba330fc9447a0R92-R93
Type of change
Tests