[BUG] MIMXRT1176 CLOCK_GetRootClockFreq returns wrong frequency when post divider is 1

[ChristianMosbach]

Describe the bug CLOCK_GetRootClockFreq returns wrong frequency when post divider is set to divide by 1 (0b11)

To Reproduce

• Environment (please complete the following information):
  • Tag/Commit hash: [MCUX_2.11.0]
  • Toolchain: [ARMGCC 10.3-2021.07]
  • Board/SoC: [MIMXRT1176 on MIMXrt1170-EVK]
  • Example [iled_blinky_cm7]
• Steps to reproduce the behavior:
  1. In MCUXpresso use the excample MIMXRT1176 iled_blinky_cm7
  2. Configure CortexM7 core root clock to ARM_PLL_CLK and the Divider to 3
  3. Configure ArmPLL to 1875 and the Post Divider to 1
  4. Update Code
  5. Set a breakpoint board/clock_config.c on the line with "SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M7);"
  6. Read out SystemCoreClock. On My system says its 37500000.

Expected behavior SystemCoreClock should be 600000000

Screenshots and console output

Additional context CLOCK_GetPllFreq(kCLOCK_PllArm) does not calculate the post divider correctly. if post divider is 1, the register holds 0x3. fsl_clock.c line 1442 shifts postDiv to 0x10, But the divider for the calculation should be 1.

[mcuxsusan]

Thanks for reporting the issue, the bug fix will be available soon.

[mcuxsusan]

Hi @ChristianMosbach, please check the fix in latest main https://github.com/NXPmicro/mcux-sdk/commit/1389627cb281fc5515d37fe9f4e05522518ca925