Add effective frequency

[leogx9r]

Like HWiNFO64, the popular monitoring tool for Windows, this patch adds support for reading the cores' effective frequency or multiplier by making use of the undocumented MSR, 0xC0010293.

This MSR was found by reverse-engineering Ryzen Master, the AMD software for Windows overclocking and monitoring of Zen based processors. Although this MSR is undocumented, since it is used in software written by AMD themselves, it is safe to assume it is accurate.

The MSR returns two things, the FID or effective frequency ID and the FDID. The FID, when divided by the FDID for a core, produces a frequency in increments of 200 MHz -- the effective frequency.

[ocerman]

@leogx9r It works! Thanks, merged.

BTW, about that reverse-engineered Ryzen Master: Do you whether there was also discovered anything else?

[irusanov]

I've personally found 0xC0010293 defined as MSR_AMD_PSTATE_F17H_BOOST in another github repo. It has the same bit definition as the rest of the PStates.

[leogx9r]

@leogx9r It works! Thanks, merged.

BTW, about that reverse-engineered Ryzen Master: Do you whether there was also discovered anything else?

Ryzen master has many, many things in regards to the processors in the Zen family. So far I've reversed several bits of information including:

• Reading PBO limits -- both the "fused" values on the chip and the actual in-use values (PPT, TDC, EDC, TDP, AutoOC, PBO Scalar)

• Setting PBO limits (All the above)

• Additional voltages ( VID, VDDP, VDDG, VDDIO, VTT )

• Reading memory timings ( FCLK, MCLK, primary & secondary timings and CAD Bus settings resistances )

• Reading "preferred cores" via CPPC2 and performance rankings of the cores.

The problem with most of these things is that it requires, like zenpower, access to the SMN, both for reading and writing which can only be done via a kernel driver since the kernel doesn't expose amd_smn_read and nifty tools like rdmsr and wrmsr don't exist for it.

This was all just after a few hours reading the assembly, so I know how they're done but re-implementing them is a bit complicated for some of them as they directly write "magic" values to the SMN -- which I'm uncomfortable with as I can't easily reprogram my BIOS if I fail and have no idea if a CMOS reset will clear any "messed up" SMN values.

So for now, I've taken the liberty to implement particular parts that are relatively easy parts first and work more on reversing later on, with the (idealistic) goal of implementing most, if not all of Ryzen Master's features directly from Linux but I've already implemented a basic driver that exposes the DRAM timings via the SMN as sysfs read-only variables.

[irusanov]

Any SMN commands I've tried are not permanent. Sometimes it requires a full powerdown cycle, but most of the times a simple reboot works.

SMU addresses are different for each generation, also most of them support several mailboxes (SMN sets of addresses). Setting OC frequency, OC VID and PBO limits work and I've figured them out for most of the CPUs. Implementing all the controls for Linux would be cool, though.

I've taken one of the older python-based Zenstate for Linux and extended it with a GUI and support for newer generations, but still not complete. I'm not that familiar with Python either.

You can access the SMN via the standard PCI Configuration interface.

[leogx9r]

Alright that definitely gives me a bit more confidence for experimenting then.

EDIT: And yes, thankfully Ryzen Master has all the SMN commands for each generation in them so it's just a matter of reversing each family.