The main issue solved in this merge request is one I've introduced.
The description of a register field was placed with the wrong field in the generated code.
So the description of field 0 was the description of n-1.
And the cleanup of the white spaces at some generated lines.
And in the VHDL code there where lines where there was a space before the '(' and lines without.
e.g. std_logic_vector(...) and std_logic_vector (...)
I'm more used to see VHDL without a space. If you prefer with a space, I can change it.
Andreas,
The main issue solved in this merge request is one I've introduced.
The description of a register field was placed with the wrong field in the generated code. So the description of field 0 was the description of n-1.
And the cleanup of the white spaces at some generated lines.
And in the VHDL code there where lines where there was a space before the '(' and lines without. e.g.
std_logic_vector(...)andstd_logic_vector (...)I'm more used to see VHDL without a space. If you prefer with a space, I can change it.Br